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[VHDL-FPGA-Verilog] USB_1.1IP核 DL : 0: 这是USB的一个机遇FPGA的IP核设计。欢迎大家使用
Date : 2011-12-31 Size : 11.97mb User : steeflian
[VHDL-FPGA-Verilog] pci_vhdl DL : 0: PCI的VHDL源码希望对大家有用！-PCI VHDL source hope useful for all!
Date : 2025-12-25 Size : 27kb User : 林建加
[VHDL-FPGA-Verilog] USB 1.1 IP-CORE和设计范例 VHDL源代码 DL : 0: USB 1.1 IP-CORE和设计范例 VHDL源代码-Sample program for USB1.1 IP core design, VHDL source code
Date : 2025-12-25 Size : 416kb User : ken
[VHDL-FPGA-Verilog] usb1.1_Verilog DL : 1: usb1.1的设备控制器IP核，是用verilog硬件描述语言写的-USB1.1 IP core for device control, written with hardware describing language of Verilog.
Date : 2025-12-25 Size : 128kb User : 李恒
[VHDL-FPGA-Verilog] USB IPcore（带说明） DL : 0: USB IPcoreIP核，包含文档（带说明）-USB IPcoreIP nuclear contains documents (with the note)
Date : 2025-12-25 Size : 399kb User : 陈友荣
[VHDL-FPGA-Verilog] USB 2.0 IP Core DL : 0: USB20的IP CORE,可以直接用在SOPC下，自动完成全部的枚举，只需修改枚举参数即可！-USB20 IP CORE, can be directly used in SOPC, automatically complete the enumeration. only a modification of enumerated parameters can be!
Date : 2025-12-25 Size : 177kb User : 林风
[VHDL-FPGA-Verilog] USB2.0IP_core_Verilog DL : 0: 完整的用VERILOG语言开发的USB2.0 IP核源代码，包括文档、仿真文件-complete with verilog language development USB2.0 IP source code, including documentation, Simulation documents
Date : 2025-12-25 Size : 202kb User : 张清平
[VHDL-FPGA-Verilog] usb_funct[1].tar DL : 1: usb2.0的IP核，可在QuartusII或MaxPlusII环境下实现编译和生成ip核-usb2.0 IP nuclear, QuartusII or the environment under MaxPlusII compile and generate nuclear ip
Date : 2025-12-25 Size : 177kb User : 刘洋
[VHDL-FPGA-Verilog] USB_2-0_Host_IP_Core DL : 0: this come from alter ,you can look and find it on line about USB
Date : 2025-12-25 Size : 87kb User : fff
[VHDL-FPGA-Verilog] USB DL : 0: 用VHDL实现的USB IP核，大家可以参考下-Use VHDL to achieve USB IP core, we can refer to the following
Date : 2025-12-25 Size : 1.09mb User : 蔡飞
[VHDL-FPGA-Verilog] usb11 DL : 0: 基于verilog HDL的一个USB 1.1的IP 核，内有详细文档说明。-Verilog HDL based on a USB 1.1 of the IP core, which has detailed documentation.
Date : 2025-12-25 Size : 405kb User : 戴求淼
[VHDL-FPGA-Verilog] can DL : 0: 基于Verilog HDL 的一个CAN总线IP核。-Based on Verilog HDL a CAN bus IP core.
Date : 2025-12-25 Size : 87kb User : 戴求淼
[VHDL-FPGA-Verilog] 1 DL : 1: 15个免费的IP核 usb11,i2c,pci_core,video_compression_systems等等.-15 free IP core usb11, i2c, pci_core, video_compression_systems and so on.
Date : 2025-12-25 Size : 2.52mb User : likufan
[VHDL-FPGA-Verilog] usb_latest.tar DL : 0: 用VHDL语言编写的USB 2.0IP核。USB 2.0的传输速率是高速率480 Mb/s，需要再外扩一个PHY。-This is a USB 2.0 compliant core，USB 2.0 allows data transfers of 480 Mb/s. Because of the high interface speed, an external PHY will be required with this core.
Date : 2025-12-25 Size : 192kb User : liang
[VHDL-FPGA-Verilog] usb DL : 0: USB完整代码包括vhdl和verilog两种-usb ip core
Date : 2025-12-25 Size : 254kb User : 王强
[VHDL-FPGA-Verilog] verilog-usb--protel-design DL : 1: 基于FPGA的usb2.0 ip核设计，所用的语言是verilog-FPGA-based usb2.0 ip core design, the language used is the verilog
Date : 2025-12-25 Size : 52kb User : 唐明桂
[VHDL-FPGA-Verilog] USB_Verilog_IP DL : 0: USB IP核VHDL源码(使用VHDL实现的USB IP core)-USB IP core VHDL source
Date : 2025-12-25 Size : 140kb User : xsp
[VHDL-FPGA-Verilog] USB2.0-IP DL : 0: USB2.0 IP核源代码，经典好用！写这么多真没意思！-USB 2.0 IP core source code, easy to use classic! Write so really boring!
Date : 2025-12-25 Size : 224kb User : sulianghe
[VHDL-FPGA-Verilog] usb DL : 0: USB的verilog IP模块，经过DesignCompiler综合验证-USB-verilog IP module, comprehensive verification through DesignCompiler
Date : 2025-12-25 Size : 56kb User : sj
[VHDL-FPGA-Verilog] IP DL : 0: USB+UART+I2C+VGA+ARM7+MC8051 altera IP核-USB+UART+I2C+VGA+ARM7+MC8051 Verrlog VHDL
Date : 2025-12-25 Size : 3.63mb User : 刘春焱

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