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[VHDL-FPGA-Verilog] USB 1.1 IP-CORE和设计范例 VHDL源代码 DL : 0: USB 1.1 IP-CORE和设计范例 VHDL源代码-Sample program for USB1.1 IP core design, VHDL source code
Date : 2025-12-19 Size : 416kb User : ken
[VHDL-FPGA-Verilog] usb1.1_Verilog DL : 1: usb1.1的设备控制器IP核，是用verilog硬件描述语言写的-USB1.1 IP core for device control, written with hardware describing language of Verilog.
Date : 2025-12-19 Size : 128kb User : 李恒
[VHDL-FPGA-Verilog] USB枚举 DL : 0: ALTERA　NIOS处理器实验，编程环境是QUARTUS，在NIOS SHELL下编译实现功能。实验USB接口-Altera NIOS processor experiments, programming environment is QUARTUS in NIOS SHELL compiler functionality. Experimental USB interface
Date : 2025-12-19 Size : 35kb User : xf
[VHDL-FPGA-Verilog] USB IPcore（带说明） DL : 0: USB IPcoreIP核，包含文档（带说明）-USB IPcoreIP nuclear contains documents (with the note)
Date : 2025-12-19 Size : 399kb User : 陈友荣
[VHDL-FPGA-Verilog] USB 2.0 IP Core DL : 0: USB20的IP CORE,可以直接用在SOPC下，自动完成全部的枚举，只需修改枚举参数即可！-USB20 IP CORE, can be directly used in SOPC, automatically complete the enumeration. only a modification of enumerated parameters can be!
Date : 2025-12-19 Size : 177kb User : 林风
[VHDL-FPGA-Verilog] USB2.0IP_core_Verilog DL : 0: 完整的用VERILOG语言开发的USB2.0 IP核源代码，包括文档、仿真文件-complete with verilog language development USB2.0 IP source code, including documentation, Simulation documents
Date : 2025-12-19 Size : 202kb User : 张清平
[VHDL-FPGA-Verilog] USB_2-0_Host_IP_Core DL : 0: this come from alter ,you can look and find it on line about USB
Date : 2025-12-19 Size : 87kb User : fff
[VHDL-FPGA-Verilog] USB DL : 0: 用VHDL实现的USB IP核，大家可以参考下-Use VHDL to achieve USB IP core, we can refer to the following
Date : 2025-12-19 Size : 1.09mb User : 蔡飞
[VHDL-FPGA-Verilog] usb_phy.tar DL : 0: Very simple USB 1.1 PHY. Includes all the goodies: serial/parallel conversion, bit stuffing/unstuffing, NRZI encoding decoding. Uses a simplified UTMI interface. Currently doesn t do any error checking in the RX section [should probably check for bit unstuffing errors]. Otherwise complete and fully functional. There is currently no test bench available. This core is very simple and is proven in hardware. I see no point of writing a test bench at this time.
Date : 2025-12-19 Size : 7kb User : eldis
[VHDL-FPGA-Verilog] usb11 DL : 0: 基于verilog HDL的一个USB 1.1的IP 核，内有详细文档说明。-Verilog HDL based on a USB 1.1 of the IP core, which has detailed documentation.
Date : 2025-12-19 Size : 405kb User : 戴求淼
[VHDL-FPGA-Verilog] can DL : 0: 基于Verilog HDL 的一个CAN总线IP核。-Based on Verilog HDL a CAN bus IP core.
Date : 2025-12-19 Size : 87kb User : 戴求淼
[VHDL-FPGA-Verilog] 1 DL : 1: 15个免费的IP核 usb11,i2c,pci_core,video_compression_systems等等.-15 free IP core usb11, i2c, pci_core, video_compression_systems and so on.
Date : 2025-12-19 Size : 2.52mb User : likufan
[VHDL-FPGA-Verilog] UART_Xilinx_vhd DL : 0: USB IPcoreIP核包含文档(带说明)-USB IPcoreIP core includes a document (with instructions)
Date : 2025-12-19 Size : 8kb User : tom
[VHDL-FPGA-Verilog] usb_latest.tar DL : 0: 用VHDL语言编写的USB 2.0IP核。USB 2.0的传输速率是高速率480 Mb/s，需要再外扩一个PHY。-This is a USB 2.0 compliant core，USB 2.0 allows data transfers of 480 Mb/s. Because of the high interface speed, an external PHY will be required with this core.
Date : 2025-12-19 Size : 192kb User : liang
[VHDL-FPGA-Verilog] usb DL : 0: USB完整代码包括vhdl和verilog两种-usb ip core
Date : 2025-12-19 Size : 254kb User : 王强
[VHDL-FPGA-Verilog] usb11_latest.tar DL : 0: its all about implementation of usb 1.1 core
Date : 2025-12-19 Size : 361kb User : cooldude
[VHDL-FPGA-Verilog] FT2232H_USB_Core DL : 0: 在FPGA外扩用FT2232 实现UART TO USB 2.0 的通信。-The FT2232H is a USB2.0 Hi-Speed USB Device to FIFO IC. This core allows the use of this chip with an FGPA design in high speed FT245 style synchronous FIFO mode. Data rates up to 25 mbytes/s can be achieved. The core has internal FIFOs on the receive and transmit for improved throughput. For more information see FTDI s appnote "AN_130_FT2232H_Used_In_FT245 Synchronous FIFO Mode.pdf" Included: VHDL core, NIOS test application, PC test application
Date : 2025-12-19 Size : 6kb User : 李涛
[VHDL-FPGA-Verilog] verilog-usb--protel-design DL : 1: 基于FPGA的usb2.0 ip核设计，所用的语言是verilog-FPGA-based usb2.0 ip core design, the language used is the verilog
Date : 2025-12-19 Size : 52kb User : 唐明桂
[VHDL-FPGA-Verilog] USB_Verilog_IP DL : 0: USB IP核VHDL源码(使用VHDL实现的USB IP core)-USB IP core VHDL source
Date : 2025-12-19 Size : 140kb User : xsp
[VHDL-FPGA-Verilog] USB_Core DL : 0: USB Core in Verilog for implementation into FPGA devices.
Date : 2025-12-19 Size : 4.93mb User : flame

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