Search - traffic light segment

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[VHDL-FPGA-Verilog] jtd1 DL : 0: 交通灯实现的源程序，可实现简单的交通灯控制，用七段数码管显示时间-The realization of the source of traffic lights, can be a simple traffic light control, with Seven-Segment LED Display Time
Date : 2025-12-21 Size : 1kb User : 老大
[VHDL-FPGA-Verilog] traffic_Light DL : 0: 模拟十字路口交通灯的VHDL程序，附有用与配合ModelSim的仿真程序。内容：交通灯设计（1）A，B方向各有红，黄，绿灯，初始态全为红灯，之后东西方向通车，绿灯灭后，黄灯闪烁，各路口通车时间为30秒，由两个七段数码管计数，当显示时间小于3秒的时候通车方向黄灯闪烁（2）系统时钟1KHz，黄灯闪烁时钟要求为2Hz，七段码管的时间显示为1Hz脉冲，即1秒递减一次，在显示时间小于3秒时，通车方向的黄灯以2Hz的频率闪烁，系统中加入外部复位信号。（3）用ModelSim做仿真 -VHDL program simulate the crossroads of traffic lights, accompanied with the ModelSim simulation program. : Traffic light design (1) A, B, the direction of each red, yellow, green, and the initial state of all the red, the east-west direction after the opening of the green off, flashing yellow light, the intersection open to traffic for 30 seconds by two seven segment LED count, (2) the opening of the direction of the yellow light flashes when the display time is less than 3 seconds when the system clock 1KHz, flashing yellow light clock requirements for 2Hz, seven segment tubes 1Hz pulse, that is a seconds, decreasing the display time of less than 3 seconds, the opening direction of the yellow light is flashing, the system by adding an external reset signal frequency of 2Hz. (3) with ModelSim simulation
Date : 2025-12-21 Size : 1kb User : 陈若耿
[VHDL-FPGA-Verilog] jiaotongdeng DL : 0: VHDL语言实现模拟交通灯的运行，55s红，5s黄，30s绿灯切换，用led显示，同时在数码管上显示倒计时。内含详细说明以及仿真图-use VHDL language, traffic light and display time on segment-led
Date : 2025-12-21 Size : 1.51mb User : maxiaobo
[VHDL-FPGA-Verilog] jiaotongdeng_fuza DL : 0: 本文基于FPGA技术的发展和Quartus II开发平台，实现路口交通灯控制器是一种解决方案。使用Verilog HDL硬件描述语言来描述语言程序的分频器模块，控制模块，数据解析模块，显示译码模块和段选位选模块，五个模块，并通过各个模块程序之间的端口合理连接和协调，成功设计出交通信号灯控制电路。在Quartus II环境下模拟，生成顶层文件下载后，在FPGA EP2C5Q208器件进行验证。(Based on the development of FPGA technology and the development platform of Quartus II, the realization of traffic lights controller at intersection is a solution. The Verilog HDL hardware description language is used to describe the frequency divider module of the language program, the control module, the data parsing module, the decoding module and the segment selection and selection module, five modules, and the communication and communication light control circuit is successfully designed through the reasonable connection and coordination of the ports between each module program. In the Quartus II environment, the simulation generates top-level files after downloading in FPGA The EP2C5Q208 device is verified.)
Date : 2025-12-21 Size : 5.35mb User : 威威谈谈