Search - tip - CodeBus

Search - tip - List

[VHDL-FPGA-Verilog] bahe DL : 0: 设计四拔河游戏机 1、设计一个能进行拔河游戏的电路。 2、电路使用15个(或9个)发光二极管，开机后只有中间一个发亮，此即拔河的中心点。 3、游戏双方各持一个按钮，迅速地、不断地按动，产生脉冲，谁按得快，亮点就向谁的方向移动，每按一次，亮点移动一次。 4、亮点移到任一方终端二极管时，这一方就获胜，此时双方按钮均无作用，输出保持，只有复位后才使亮点恢复到中心。 5、用数码管显示获胜者的盘数。教学提示: 1、按钮信号即输入的脉冲信号，每按一次按钮都应能进行有效的计数。 2、用可逆计数器的加、减计数输入端分别接受两路脉冲信号，可逆计数器原始输出状态为0000，经译码器输出，使中间一只二极管发亮。 3、当计数器进行加法计数时，亮点向右移；进行减法计数时，亮点向左移。 4、由一个控制电路指示谁胜谁负，当亮点移到任一方终端时，由控制电路产生一个信号，使计数器停止计数。 5、将双方终端二极管“点亮”信号分别接两个计数器的“使能”端，当一方取胜时，相应的计数器进行一次计数，这样得到双方取胜次数的显示。 6、设置一个“复位”按钮，使亮点回到中心，取胜计数器也要设置一个“复位”按钮，使之能清零。 -design a tug-of-war game, can design a game of tug of war circuit. 2, circuit use 15 (or 9), light-emitting diodes, come only among a shiny, namely, the center of tug-of-war. 3, the game with a two button rapidly and continuously pressed, have a pulse, who by fast, Who bright spots on the move, every time, a bright spot in Mobile. 4, the party moved to highlight terminal diode, on the winning side, this time the two sides had no effect buttons, to maintain output, so after only bright spot reduction restored to the center. 5, digital Display won the bookkeeping. Teaching Tip : one, that the button signal input pulse signal every time the button should be able to effectively counter. 2, with reversible counter, plus or minus count input to receive two pulse signal, reversible counter to the
Date : 2025-12-23 Size : 286kb User : 万金油
[VHDL-FPGA-Verilog] jianpancaomiao DL : 0: 经过对系统做需求分析，详细功能设计、编码，模块连接，并利用FPGA实现相应的功能，经过波形仿真、下载调试，验证了设计方案的可行性及实现方法的有效性，基本实现了系统的要求。-Microwave controller system is a utility-type system that includes not only the function of simple operation, but also good effect of cook. According to fixed routine, you can cook some homely dish via taking different time and different level firepower to heat, and this can not only save time, but also save energy. It mainly includes a couple of modules as follows: input module, control module and display module. Input module fulfills key-press scanning and keyboard decoding, control module includes status switching control, data loading, cook time, temperature control, sound effect tip and so on, display module comes down to display coding decipher and the flashing of indicator light. Through the analysis of requirement, detailed function design, coding, module connection, using FPGA to fulfill relevant function.
Date : 2025-12-23 Size : 98kb User : 仇斌杰
[VHDL-FPGA-Verilog] 8421ma-zhuan-huan-cheng-yu-san-ma- DL : 0: 设计一个串行的8421BCD码转换成串行余3码的逻辑系统。基本要求如下：8421码作为串行输入，余三码作为串行输出。每四个时钟周期完成一位十进制的转换；提示：从8421码到余三码的转换过程中寻找规律，继而完成状态设计过程；-Design a serial 8421BCD code to convert the serial logic systems of more than three yards. The basic requirements are as follows: 8421 yards as a serial input, more than three yards as a serial output. Every four clock cycles to complete the conversion of a decimal Tip: to find the law from 8421 yards to more than three yards of the conversion process, then the completion status of the design process
Date : 2025-12-23 Size : 43kb User : 李
[VHDL-FPGA-Verilog] DDS DL : 0: 基于FPGA的数字信号合成器（DDS）,采用VHDL语言编写，能够实现正弦波、三角波、方波、锯齿波这四种波形的产生。提示：最后输出的模块是串行DA，可根据具体情况更改驱动。-Digital synthesizer (DDS) based on FPGA, using VHDL language, to achieve sine wave, triangle wave, square wave, sawtooth waveform generation four. Tip: The last output module is a serial DA, may change depending on the driving situation.
Date : 2025-12-23 Size : 2.67mb User : 康二栋