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[VHDL-FPGA-Verilog] pinlvji 频率计VHDL编程 DL : 0: 频率计VHDL编程。设计一个4位数字显示的十进制频率计，其测量范围为1MHz，测量值通过4个数码管显示以8421BCD码形式输出，可通过开关实现量程控制，量程分10kHz、100kHz、1MHz三档(最大读数分别为9.999kHz、99.99kHz、999.9kHz)；当输入信号的频率大于相应量程时，有溢出显示。 -Cymometer VHDL programming. Design of a 4-digit decimal display frequency, the measurement range of 1MHz, the measured value through the four LED 8421BCD code shows the form of output can be controlled through the switch range, range at 10kHz, 100kHz, 1MHz Three (maximum reading were 9.999kHz, 99.99kHz, 999.9kHz) when the input signal is greater than the corresponding frequency range, it shows overflow.
Date : 2012-01-11 Size : 88.05kb User : testsb
[VHDL-FPGA-Verilog] VHDL_Development_Board_Sources DL : 0: 这是我最近买的一套CPLD开发板VHDL源程序并附上开发板的原理图,希望对你是一个很好的帮助!其中内容为:8位优先编码器,乘法器,多路选择器,二进制转BCD码,加法器,减法器,简单状态机,四位比较器,7段数码管,i2c总线,lcd液晶显示,拨码开关,串口,蜂鸣器,矩阵键盘,跑马灯,交通灯,数字时钟.-which I have recently bought a CPLD Development Board VHDL source code accompanied the development of the plate diagram, You hope to be a good help! which states : eight priority encoder, multipliers, multi-path selectors, BCD binary switch, adder, subtraction device, the simple state machine, four comparators, seven of the digital control, i2c bus, lcd LCD allocated code switches, serial port, the buzzer sounded, matrix keyboards, Bomadeng, traffic lights, Digital Clock.
Date : 2025-12-30 Size : 4.43mb User : Jawen
[VHDL-FPGA-Verilog] VHDL-ysw DL : 0: Date : 2025-12-30 Size : 2kb User : 杨仕伟
[VHDL-FPGA-Verilog] vhdl_i2c DL : 0: 7． IIC 接口EEPROM 存取实验按动开发板键盘某个键CPLD 将拨码开关的数据写入EEPROM 的某个地址，按动另外一个键，将刚写入的数据读回CPLD，并在数码管上显示。帮助读者掌握I2C 的总线协议和EEPROM 的读写方法。-7. IIC EEPROM Access Interface Development Board experimental pressed a button keyboard CPLD code will go into the data switch E EPROM a certain address, pressed another button, just write the data back to reading CPLD, and the digital pipe show. To help readers master the I2C bus protocol and EEPROM read and write methods.
Date : 2025-12-30 Size : 410kb User : 赵海东
[VHDL-FPGA-Verilog] 6FloorLift DL : 0: 设计一个6层电梯控制器。电梯控制器是按照乘客的要求自动上、下的装置。 1、每层电梯入口处设置上下请求开关，电梯内设有顾客到达层次的停站请求开关。 2、设有电梯所处位置指示装置以及电梯运行模式（上升或者下降）指示装置。 3、电梯每秒升降一层楼。 4、电梯到达有停站请求的楼层，经过1秒电梯门打开，开门4秒后，电梯门关闭（开门指示灯灭），电梯继续运行，直至执行完最后一个请求信号后停留在当前层。 5、电梯能记忆电梯内外所有请求信号，并按照电梯运行规则按顺序响应，每个请求信号保留至有电梯响应后消除。 6、初始状态为一层开门，第一层不用向下开关，最高层不用向上开关。 7、电梯运行规则：当电梯上升时，只响应比电梯所在位置高的上楼请求信号，由下而上逐个执行，直到最后一个上楼请求执行完毕；如果高层有下楼请求，则直接升到下楼请求的最高楼层，然后进入下降模式。当电梯处于下降模式时与上升正好相反。 -design of a six-story elevator controller. Elevator Controller in accordance with the requirements of passengers automatically, the device. 1, installed on each floor elevator entrance next request switches, elevator begins to reach the level of customer stops request switch. 2, the location of elevator and escalator installations instructions operation mode (up or down) device instructions. 3, Elevator per second floor landing. 4, the lift reached a request stops floors seconds after an elevator doors open door four seconds later, elevator doors closed (to open the door to eliminate light), the continued operation of the lift, End until the implementation of the final request for a signal to stay in the current layer. 5, the lift will lift internal and external memory signal to all reques
Date : 2025-12-30 Size : 2kb User : zheng
[VHDL-FPGA-Verilog] encoder DL : 0: VHDL实现循环码编码，设计了三个单元。switch是一个开关，shifter是移位寄存器，encoder是主体。-VHDL realization of cyclic code encoding, designed three modules. switch is a switch, shifter is the shift register, encoder is the main.
Date : 2025-12-30 Size : 2kb User : 王三一
[VHDL-FPGA-Verilog] qichewendengVHDLsheji DL : 0: 用4个开关作为汽车控制信号,分别为：左拐、右拐、故障和刹车-4 switch used as a motor control signal, respectively, as follows: left, right, brake failure and
Date : 2025-12-30 Size : 1kb User : 赵国良
[VHDL-FPGA-Verilog] zmd_1 DL : 0: 用VHDL描述一个由8个发光二极管组成的走马灯。有系统复位。单点移动模式：一个点在8个发光二极管上来回的亮。幕布式：从中间两个点，同时向两边依次点亮直至全亮，然后再向中间点灭，依次往复。采用拨码开关转换显示模式。 -Use VHDL to describe an 8-digit LED lantern. System has reset. Single point of mobile model: a point in eight light-emitting diode on the light back and forth. Curtain-style: from between the two points, at the same time on both sides until the whole bright light followed, and then point out to the middle, followed by reciprocating. Using dial code conversion display mode switch.
Date : 2025-12-30 Size : 1kb User : wx
[VHDL-FPGA-Verilog] VGA DL : 0: VGA显示的例子（VHDL语言），实现彩条显示，按键reset实现切换功能。-VGA display example (VHDL language), to achieve color display, reset button switch function to achieve.
Date : 2025-12-30 Size : 334kb User : 侯典华
[VHDL-FPGA-Verilog] diantikongzhiqi DL : 0: 本设计是本人的课程设计，基于VHDL的电梯控制器的设计，能够实现12层电梯控制，上下开关，关门延时，提前关门，状态显示，通过波形仿真进行观看结果-The design is my curriculum design, VHDL-based elevator controller design, can achieve 12-storey elevator control, up and down switch, closing delay, early closing, the status display, through to watch the results of waveform simulation
Date : 2025-12-30 Size : 67kb User : polly
[VHDL-FPGA-Verilog] lift_code_verilog DL : 1: 实现一个4层楼的单电梯控制系统。门可以自动开关也可以手动开关。代码可综合，无多驱动现象。-Realize a 4-story single-elevator control system. Door can automatically switch can also manually switch. Code can be integrated, no more than drive the phenomenon.
Date : 2025-12-30 Size : 3kb User : 幻婳
[VHDL-FPGA-Verilog] freq DL : 1: 智能频率计 1. 频率测量范围为1Hz~1MHz 2. 当频率在1KHz以下时采用测周方法其它情　　　　况采用测频方法.二者之间自动转换 3. 测量结果显示在数码管上,单位可以是Hz（Ｈ）、　　　KHz（ＡＨ）或MHz（ＢＨ）。４. 测量过程不显示数据，待测量结果结束后，直接显示结果。 -Intelligent frequency meter 1. Frequency measurement range of 1Hz ~ 1MHz 2. When the frequency of 1KHz weeks following measurement methods used in other circumstances the use of frequency measurement methods. Automatically switch between the two 3. Measurement results have shown that in the digital control, the unit can be Hz (H), KHz (AH) or MHz (BH). 4. Measurement process does not display data until after the end of the measurement results, the direct result will be displayed.
Date : 2025-12-30 Size : 233kb User : 谭超
[VHDL-FPGA-Verilog] mux21a DL : 0: 二选一多路选择开关，实现对信号的采集，分类。-Second, the election more than one way selector switch, to achieve signal acquisition, classification.
Date : 2025-12-30 Size : 103kb User : weigong
[VHDL-FPGA-Verilog] vhdl4 DL : 0: 数字密码锁： 1.系统具有预置的初始密码“00000001”。 2.输入密码与预存密码相同时，开锁成功，显示绿灯，否则开锁失败，显示红灯。 3.具有修改密码功能。修改密码时，先开锁，开锁成功才可以修改。 4.系统同时具有关锁功能。关锁后，显示红灯。 5.密码由拔码开关表示，开锁由按键表示。 6具有一个复位按键。按键后，回到初始状态。 -The number of locks: 1. System has preset the initial password 00000001. 2. Enter the password with the stored password is the same, unlock success, showing a green light, or else unlock the failure to show a red light. 3. With the Change Password function. Modify password, to unlock, unlock success only can be amended. 4. System lock clearance at the same time. Clearance after the lock, showing a red light. 5. Password code switch from Stubbs said that by the keys that unlock. 6 has a reset button. Button to return to the initial state.
Date : 2025-12-30 Size : 246kb User : 宫逢源
[VHDL-FPGA-Verilog] s3esk_rotary_encoder_interface DL : 0: Xilix spartan 3E 旋转编码器接口,脉冲方向识别,AB脉冲滤波 Rotary Encoder Interface Demonstrates how to use the rotary encoder portion of the rotary pushbutton switch.-Xilix spartan 3E rotary encoder interface, pulse direction identification, AB pulse filter Rotary Encoder InterfaceDemonstrates how to use the rotary encoder portion of the rotary pushbutton switch.
Date : 2025-12-30 Size : 273kb User : weihua yuan
[VHDL-FPGA-Verilog] SF_table_interface DL : 0: switch fabric部分代码: fabric和table management 的数据交换. Mac address 从afifo输入, 查询的结果:output port number 存于pfifo中-switch fabric part of the code: fabric and table management data exchange. Mac address from afifo input, the results of inquiries: output port number stored in Medium pfifo
Date : 2025-12-30 Size : 2kb User : 无影
[VHDL-FPGA-Verilog] VHDL(LOCK) DL : 0: 数字密码锁的设计与实现一．实验目的 1. 学习VHDL的综合设计应用 2. 学习数字密码锁的设计二．实验内容设计一个数字密码锁，对其编译，仿真，下载。数字密码锁具体要求如下： 1.系统具有预置的初始密码“00000001”。 2.输入密码与预存密码相同时，开锁成功，显示绿灯，否则开锁失败，显示红灯。 3.具有修改密码功能。修改密码时，先开锁，开锁成功才可以修改。 4.系统同时具有关锁功能。关锁后，显示红灯。 5.密码由拔码开关表示，开锁由按键表示。 6具有一个复位按键。按键后，回到初始状态。 -VHDL Digital Design and Implementation of lock 1. Purpose of the experiment 1. VHDL Integrated Design and Application of Learning 2. Learning digital code lock design 2. Experimental content Design a digital lock on their compilation, simulation, download. Digital code lock specific requirements are as follows: 1. System has preset the initial password "00000001." 2. Enter the same password with the stored password, unlock successful, a green light, or unlock failed to show a red light. 3. With the change password function. Modify password, the first lock, unlock success can modify. 4. The system also has off lock. Shut up after the red light. 5. The password code from the pull switch that unlock the keys, said. 6 has a reset button. Button, the return to initial state.
Date : 2025-12-30 Size : 18kb User : 爱好
[VHDL-FPGA-Verilog] VHDL-dianti DL : 0: 高楼电梯自动控制系统(Windows平台上运行的ispLEVER编程软件。 ): 1统控制的电梯往返于1-9层楼。 2客要去的楼层数可手动输入并显示（设为A数）。 3梯运行的楼层数可自动显示（设为B数）。 4A>B时，系统能输出使三相电机正转的时序信号，使电梯上升；当A<B时，系统能输出使三相电机反转的时序信号，使电梯下降；当A=B时，系统能输出使三相电机停机的信号，使电梯停止运行并开门； 5是上升还是下降各层电梯门外应有指示，各层电梯门外应有使电梯上升或下降到乘客所在楼层的控制开关。注：此为word文档，但里面有源代码。-High-rise elevator control system (Windows platform programming software running on the ispLEVER. ): An elevator control system and from 1-9 floors. 2, the number of passengers going to the floor can manually enter and display (Make A number). 3 ladder run automatically display the number of floors (Set B number). 4A> B, the system can output three-phase motor is transferred to the timing signal to lift up When A <B, the system can output three-phase motor to reverse the timing signal to the lift down When A = B, the system can output a signal to shut down three-phase motor, so that the lift stops and open the door 5 is increasing or decreasing the lift on each floor outside the door should be directed, due to lift on each floor outside the elevator up or down to the floor where the passenger control switch. Note: This is a word document, but inside the source code.
Date : 2025-12-30 Size : 34kb User :
[VHDL-FPGA-Verilog] VHDL-3BCD DL : 0: 3位BCD码的计数显示电路。BCD码计数电路从0计到9然后返回到0从新计数。3位BCD码计数器可以实现从0到999的十进制计数。要将计数过程用七段显示LED数码管显示出来，这里采用动态分时总线切换电路对数码管进行扫描，对数码管依次分时选中进行输出计数的个、十、百位的数据。-3 BCD code count display circuit. BCD code counting circuit count from 0 to 9 and then back to 0 from the new count. 3 BCD code counter can be achieved from 0 to 999 decimal count. Counting process with seven segment displays to LED digital tube displays, where dynamic time-sharing digital bus switch circuit to scan, followed by time-sharing of digital output selected for a count of ten, hundred bits of data.
Date : 2025-12-30 Size : 55kb User : will li
[VHDL-FPGA-Verilog] vhdl-code-for--A-HIGH-SPEED-SYMMETRIC-CROSSBAR-SW DL : 0: vhdl code for A HIGH SPEED SYMMETRIC CROSSBAR SWITCH-vhdl code for A HIGH SPEED SYMMETRIC CROSSBAR SWITCH
Date : 2025-12-30 Size : 13kb User : a.arezoo60

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