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[VHDL-FPGA-Verilog] SSMS DL : 0: 汇编实习作业汇编语言实现的学生信息管理系统-Compilation of assembly language to achieve practical operation of Student Information Management System
Date : 2025-12-19 Size : 2kb User : 刘海
[VHDL-FPGA-Verilog] tushuguan DL : 0: --功能描述 --1 刷卡后产生与本人身份唯一对应的串行二进制码元序列，作为模拟系统的输入信号（此处不妨设为8位学生学号）。 --2 经过串并转换，序列变成一个8位二进制数。 --3 遍历预先存储在rom中的学号信息，逐一和这个8位数相比较，如果有相匹配的信息，显示欢迎字样（此处用一个高电平表示），同时打开栅栏门（也用一个高电平表示）。 -- Functional Description- 1 credit card and identity generated only the corresponding element of the serial binary code sequence, as a simulation system of the input signal (in this case may be set to No. 8 students).- 2 after a string and conversion into a sequence of 8-bit binary number.- 3 pre-stored in the rom traversal of the Student ID information, one by one and compared to the 8-digit, if there is match the message that welcomes the word (here, said with a high), at the same time open the gate ( also expressed a high level).
Date : 2025-12-19 Size : 1kb User : leizi
[VHDL-FPGA-Verilog] FPGA_radar DL : 1: 优秀硕士论文，基于FPGA的雷达信号模拟器设计，对学FPGA的，特别是学雷达的同学有很好的参考价值-Outstanding master s thesis, based on radar signal simulator FPGA design, FPGA-on study, in particular the study of radar has a good reference Student Value
Date : 2025-12-19 Size : 732kb User : zhang
[VHDL-FPGA-Verilog] 03VHDL_Plaquette DL : 0: Course on Vhdl langage allow mainly student who want to learn and understand each elements of each code source written in Vhdl
Date : 2025-12-19 Size : 131kb User : Baba
[VHDL-FPGA-Verilog] ModelSimSETutorialFromTainwan DL : 0: 来自台湾一个大学生写的modelsim se的教程，相当实用，中文。-A college student from Taiwan wrote modelsim se of course, very practical, Chinese.
Date : 2025-12-19 Size : 351kb User : 小泉儿
[VHDL-FPGA-Verilog] show_numbers DL : 0: 在八位七段数码显示管上显示8位学号，要显示的学号可以在程序内改。-In the eight seven-segment digital display tube display 8 Student ID, Student ID to be displayed can be changed within the program.
Date : 2025-12-19 Size : 237kb User : lzj
[VHDL-FPGA-Verilog] Multiplier_Solution DL : 0: this implemented multilplier in vhdl.this source code is useful for computer student and hardware engineering.-this is implemented multilplier in vhdl.this source code is useful for computer student and hardware engineering.
Date : 2025-12-19 Size : 184kb User : Mohammad
[VHDL-FPGA-Verilog] VHDLquickstart DL : 0: Quick introduction to VHDL – basic language concepts – basic design methodology • Use The Student’s Guide to VHDL or The Designer’s Guide to VHDL – self-learning for more depth – reference for project work-Quick introduction to VHDL – basic language concepts – basic design methodology • Use The Student’s Guide to VHDL or The Designer’s Guide to VHDL – self-learning for more depth – reference for project work
Date : 2025-12-19 Size : 79kb User : yag
[VHDL-FPGA-Verilog] 6fifo DL : 0: 入门omnet++,omnet++仿真实验，欢迎大家一起交流。-It is very useful for student who study omnet++.
Date : 2025-12-19 Size : 475kb User : 刘小玉
[VHDL-FPGA-Verilog] lab1_VHDL DL : 0: lab VHDL for student enjoy it
Date : 2025-12-19 Size : 51kb User : nguyen tien chuan
[VHDL-FPGA-Verilog] Digital_System_Design_with_SystemVerilog(draft).ra DL : 0: This book is intended as a student textbook for both undergraduate and postgraduate students.-This book is intended as a student textbook for both undergraduate and postgraduate students. The majority of Verilog and SystemVerilog books are aimed at practicing engineers. Therefore, some features of SystemVerilog are not described at all in this book. Equally, aspects of digital design are covered that would not be included in a typical SystemVerilog book.
Date : 2025-12-19 Size : 1.79mb User : jiaquan
[VHDL-FPGA-Verilog] Chapter1_edu DL : 0: it is about power electronics for the student from university lecture notes-it is about power electronics for the student from university lecture notes...
Date : 2025-12-19 Size : 205kb User : ck
[VHDL-FPGA-Verilog] HW3 DL : 0: Write VHDL codes to model an 8-bit counter that counts every second. It counts from your last two digits of your student ID to your next two digits of your student ID. If the last two digits are greater than the next two digits, the counters counts down otherwise, it counts up. The counter should have asynchronous set input to set the count to your last two digits of your student ID, synchronous clear input to clear the count to 0, and enable input to enable counting. Set input has higher priority than the clear input. For now, you may assume that the clock to the counter is a 1 Hz clock. For subsequent homework, you need to design a circuit that generates the 1 Hz clock signal from the 50 MHz system clock.-Count starts from 78 down to 56, back to 78, counts down to 56, and repeat. If the counter is cleared, count starts from 0 up to 78 and then counts down to 56, back to 78, and repeat. If the counter is set, the count sets to 78. The counter will not count when it is disabled.
Date : 2025-12-19 Size : 289kb User : XingSu
[VHDL-FPGA-Verilog] VHDL-quick-start DL : 0: description of VHDL Quick introduction to VHDL – basic language concepts – basic design methodology • Use The Student’s Guide to VHDL or The Designer’s Guide to VHDL – self-learning for more depth – reference for project work-description of VHDL Quick introduction to VHDL – basic language concepts – basic design methodology • Use The Student’s Guide to VHDL or The Designer’s Guide to VHDL – self-learning for more depth – reference for project work
Date : 2025-12-19 Size : 82kb User : lavanya
[VHDL-FPGA-Verilog] odometre DL : 0: Student project in VHDL Platform Xilinx about odometry
Date : 2025-12-19 Size : 101kb User : spifoo
[VHDL-FPGA-Verilog] PID_AN DL : 0: pid with vhdl its good for student.
Date : 2025-12-19 Size : 104kb User : saman
[VHDL-FPGA-Verilog] EDA_FOR_NEW DL : 0: 这非常适合初学者，特别是为了应付考试，它的语言简单易懂-It is very usefule for the new student to learn .The language is easy，and it is usefull for you to learn before the examtion.
Date : 2025-12-19 Size : 116kb User : chen
[VHDL-FPGA-Verilog] hw3 DL : 0: Write VHDL codes to model an 8-bit counter that counts every second. It counts from your last two digits of your student ID to your next two digits of your student ID. If the last two digits are greater than the next two digits, the counters counts down otherwise, it counts up. The counter should have asynchronous set input to set the count to your last two digits of your student ID, synchronous clear input to clear the count to 0, and enable input to enable counting. For now, you may assume that the clock to the counter is a 1 Hz clock. For subsequent homework, you need to design a circuit that generates the 1 Hz clock signal from the 50 MHz system clock.-Write VHDL codes to model an 8-bit counter that counts every second. It counts from your last two digits of your student ID to your next two digits of your student ID. If the last two digits are greater than the next two digits, the counters counts down otherwise, it counts up. The counter should have asynchronous set input to set the count to your last two digits of your student ID, synchronous clear input to clear the count to 0, and enable input to enable counting. For now, you may assume that the clock to the counter is a 1 Hz clock. For subsequent homework, you need to design a circuit that generates the 1 Hz clock signal from the 50 MHz system clock.
Date : 2025-12-19 Size : 344kb User : vinay
[VHDL-FPGA-Verilog] adder3 DL : 0: 加法计数器简单的加法计数器专用于学生学习理解-Counter counter simple addition addition dedicated to understanding student learning
Date : 2025-12-19 Size : 1kb User : 林凯
[VHDL-FPGA-Verilog] pgcd_2010 DL : 0: I m student in french hiegh school
Date : 2025-12-19 Size : 44kb User : samuel

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