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[VHDL-FPGA-Verilog] vhdl-多功能电子表 DL : 0: 这是一个用vhdl编的多功能电子秒表，可以记录几个人的时间，并且可以在跑秒的时候查看记录。。〔原创〕-This is a series with VHDL multifunctional electronic stopwatch, can be recorded by several people, and that they could run in the second examined the records. . [Original]
Date : 2025-12-15 Size : 5kb User : 王继东
[VHDL-FPGA-Verilog] 数字电子钟 DL : 0: 数字电子钟此数字电子钟具有的功能包括： 1. 计时，时、分、秒显示； 2. 十二小时与二十四小时之间的转换； 3. 上下午显示； 4. 对时、分、秒的校时功能； 5. 跑表功能。-digital electronic clock this digital electronic clock with functions include : 1. Time, hours, minutes and seconds display; 2. 12 hours with 24 hours of conversion; 3. On the afternoon show; 4. Right hours, minutes, and seconds school function; 5. Stopwatch functions .
Date : 2025-12-15 Size : 7kb User : 吴健宇
[VHDL-FPGA-Verilog] EDA_clock1 DL : 0: 电子秒表电路，可在开发版上下载运行，verlog开发-electronic stopwatch circuit may download the development version running verlog Development
Date : 2025-12-15 Size : 3.24mb User : 李佳丽
[VHDL-FPGA-Verilog] byvhdstopwatchl DL : 1: 1.高精度数字秒表（0.01秒的vhdl语言实现） 2.具有定时，暂停，按键随机存储，翻页回放功能； 3.对30M时钟分频产生显示扫描时钟 4.精度高达0.01s,并且可以通过改变主频来更改分频比和记数间隔，可控性高。 5.模块化设计，其中的许多函数可以成为vhdl语言的通用经典例子（包含分频电路设计，动态扫描时钟设计，译码电路设计，存储器设计，存储回放显示设计）-1. High-precision digital stopwatch (0.01 seconds vhdl language) 2. With a timer, suspended Random memory keys, flip playback function; 3. right 30M clock frequency scan have revealed four clock. Precision high 0.01s and and can be changed to alter the frequency than the frequency interval and Hutchison, controlled high. 5. Modular design, Many of these functions can become the common language vhdl classic examples (including sub-frequency circuit design, Dynamic scanning clock design, decoding circuit design, memory design, storage intervals showed Design)
Date : 2025-12-15 Size : 2kb User : 方周
[VHDL-FPGA-Verilog] shuzimiaobiao DL : 0: 用verilog实现了一个数字秒表的设计-verilog achieved using a digital stopwatch Design
Date : 2025-12-15 Size : 1kb User : qihuolin
[VHDL-FPGA-Verilog] watch DL : 0: vhdl语言编写的一个秒表源码，包括在LCD上显示的部分，附带TB源码，对初学者比较实用-VHDL language, a stopwatch source, including the LCD display part, incidental TB source, more practical for beginners
Date : 2025-12-15 Size : 96kb User : ronniy
[VHDL-FPGA-Verilog] stopwatch DL : 0: 电子秒表，可以显示0.01S到59’59”99.带有开始、暂停、复位于一键的控制功能。-Electronic stopwatch, can display 0.01S to 59 59 99. With a moratorium, rehabilitation located in a key control functions.
Date : 2025-12-15 Size : 1kb User : jacky
[VHDL-FPGA-Verilog] stopwatch DL : 0: 秒表可计时，用VHDL编译的源代码，从0.1到60秒计时，解压后直接用Quartus打开project即可-Stopwatch timer can be used to compile the VHDL source code, from 0.1 to 60 seconds from time, after extracting the direct use of Quartus can open the project
Date : 2025-12-15 Size : 564kb User : xie
[VHDL-FPGA-Verilog] stopwatch DL : 0: VHDL语言设计的秒表，实现计时功能，实现报时功能，并且通过硬件实验。-VHDL language design stopwatch, timer function of the realization, the realization of time functions, and through hardware experiments.
Date : 2025-12-15 Size : 1.57mb User : 王蕊
[VHDL-FPGA-Verilog] stopwatch DL : 0: Quartus II工程压缩文件，是一个典型的基于FPGA的秒表工程项目，有50MHz分频、计数、译码等模块。采用VHDL语言编写。-Quartus II project files, is a typical FPGA-based project of the stopwatch, a 50MHz frequency, counting, decoding modules. Using VHDL language.
Date : 2025-12-15 Size : 454kb User : kg21kg
[VHDL-FPGA-Verilog] StopWatch DL : 0: Verilog 编写的秒表程序，在数码管上显示，带有清0和暂停键-Stopwatch Implemented by Verilog hdl
Date : 2025-12-15 Size : 571kb User : 洪磊
[VHDL-FPGA-Verilog] stopwatch DL : 0: The program is written in verilog to accomplish functions of a stopwatch. It can be implemented in Xilinx FPGA spartan 3 board.
Date : 2025-12-15 Size : 2kb User : flyingwings
[VHDL-FPGA-Verilog] stopwatch DL : 0: 基于Xilinx Spartan3E的秒表，能实现计时两次的功能-Based on the Xilinx Spartan3E stopwatch, time to achieve the functions of the two
Date : 2025-12-15 Size : 914kb User : darkblue
[VHDL-FPGA-Verilog] stopwatch DL : 0: 基于vhdl的数字秒表，计时精度为1/100秒，最长计时时间为59分59.59秒；设有复位开关、起停开关；验证可用。-On vhdl digital stopwatch, timing accuracy of 1/100 seconds, the longest time time of 59 minutes 59.59 seconds with reset switch, start-stop switches validation is available.
Date : 2025-12-15 Size : 260kb User : ly
[VHDL-FPGA-Verilog] stopwatch DL : 0: 数字秒表的VHDL代码。当设计文件加载到目标器件后，设计的数字秒表从00-00-00开始计秒。，直到按下停止按键（按键开关S2）。数码管停止计秒。按下开始按键（按键开关S1），数码管继续进行计秒。按下复位按键（核心板上复位键）秒表从00-00-00重新开始计秒。-The VHDL code for digital stopwatch. When the design document loaded into the target device, the designed digital stopwatch count the seconds from the 00-00-00. Until you press stop key (key switch S2). Nixie tube stop count seconds. Press the start button (key switch S1), the digital control continue to count seconds. Press the reset button (core panel reset button) to restart the stopwatch count seconds from the 00-00-00.
Date : 2025-12-15 Size : 1kb User : 王唐小菲
[VHDL-FPGA-Verilog] STOPWATCH DL : 0: 是基于FPGA/CPLD的跑表程序，可以存储记录多个运动员的跑步时间，是利用VHDL语言编写的，可以有助于学习EDA技术，可以参考学习，可以帮助你完成VHDL语言的课程设计。-Is based on FPGA/CPLD s stopwatch program, many athletes can store records of running time, is the use of VHDL language, and can help to learn EDA, can refer to the study, can help you complete VHDL language curriculum design.
Date : 2025-12-15 Size : 646kb User : 王亮
[VHDL-FPGA-Verilog] stopwatch DL : 0: verilog 秒表程序用quartus 编写-Verilog stopwatch ............................................................................................
Date : 2025-12-15 Size : 421kb User : icer
[VHDL-FPGA-Verilog] stopwatch DL : 0: 用Verilog编写的秒表，可以实现计时、复位、暂停等功能。-stopwatch using Verilog language
Date : 2025-12-15 Size : 475kb User : 陈璜骁
[VHDL-FPGA-Verilog] LCD-display-stopwatch DL : 0: 用c语言写的程序，用单片机实现LCD 显示秒表的功能-With c language program, with MCU function LCD display stopwatch
Date : 2025-12-15 Size : 21kb User : 小风
[VHDL-FPGA-Verilog] Digital-stopwatch-design DL : 0: 数字秒表的设计报告，用VHDL语言编写程序，实现分析讨论中各种功能，分别进行编译并生成相应的模块，然后将这些模块连接起来形成电路图，并进行编译、仿真。-Digital stopwatch design reports, using VHDL language programming, analysis and discussion of various functions to achieve, respectively, to compile and generate the corresponding module, and then connect these modules together to form a circuit, and compiled simulation.
Date : 2025-12-15 Size : 367kb User : 吴亮

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