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[VHDL-FPGA-Verilog] VHDL-status DL : 0: VHDL状态机学习笔记,对初学者有很重要的帮助意义-VHDL state machine learning notes for beginners has a very important significance help
Date : 2025-12-24 Size : 6kb User : 陈度甫
[VHDL-FPGA-Verilog] time_run DL : 0: verilog描述年月日，小时分秒的显示，2000~2099年的万历年循环用set控制，设置状态，按一下改变一个设置，正常显示时，按set进入小时设置，依次是分钟，年，月，天（天设置带懂周变换）在设置状态，按一下ADJ，加一下，按cf就减1，同步修改显示；设置状态下，按mode键或是60秒无按键，推出设置状态，返回正常显示正常显示是，按ADJ，进行24，12小时显示切换，带AM_PM显示-Verilog description of date, hours minutes and seconds display, from 2000 to 2099 million in the calendar year cycle with set control, set the status, click to change a setting, the normal display, press set to enter the hour set, followed by minute, year, month , days (days of week settings to understand transformation zone) in the set status, click the ADJ, plus some, by cf on by 1, modify the display simultaneously settings, press mode button or no button for 60 seconds, set to launch a state, return normal display is the normal display, press ADJ, switch to 24,12-hour show, with shows AM_PM
Date : 2025-12-24 Size : 4kb User : 申刚
[VHDL-FPGA-Verilog] ledcontrol DL : 0: 该程序为用vhdl语言编写的彩灯控制程序！通过状态机实现三个彩灯的状态装换，红灯亮2秒，绿灯亮3秒，黄灯亮1秒！时钟频率为1HZ！通过该程序也可以改成交通灯的情况-The procedure for the use of VHDL language Lantern control procedures! Through the state machine to achieve the status of three lantern-for-loaded, two seconds the red light, green light is 3 seconds, 1 seconds yellow light! Clock frequency of 1HZ! Through the program can also change the situation of traffic lights
Date : 2025-12-24 Size : 1kb User : 吴明星
[VHDL-FPGA-Verilog] diantikongzhiqi DL : 0: 本设计是本人的课程设计，基于VHDL的电梯控制器的设计，能够实现12层电梯控制，上下开关，关门延时，提前关门，状态显示，通过波形仿真进行观看结果-The design is my curriculum design, VHDL-based elevator controller design, can achieve 12-storey elevator control, up and down switch, closing delay, early closing, the status display, through to watch the results of waveform simulation
Date : 2025-12-24 Size : 67kb User : polly
[VHDL-FPGA-Verilog] wb_rtc DL : 0: // -*- Mode: Verilog -*- // Filename : wb_master.v // Description : Wishbone Master Behavorial // Author : Winefred Washington // Created On : 2002 12 24 // Last Modified By: . // Last Modified On: . // Update Count : 0 // Status : Unknown, Use with caution! // Description Specification // General Description: 8, 16, 32-bit WISHBONE Master // Supported cycles: MASTER, READ/WRITE // MASTER, BLOCK READ/WRITE // MASTER, RMW // Data port, size: 8, 16, 32-bit // Data port, granularity 8-bit // Data port, Max. operand size 32-bit // Data transfer ordering: little endian // Data transfer sequencing: undefined-//-*- Mode: Verilog-*- // Filename : wb_master.v // Description : Wishbone Master Behavorial // Author : Winefred Washington // Created On : 2002 12 24 // Last Modified By: . // Last Modified On: . // Update Count : 0 // Status : Unknown, Use with caution! // Description Specification // General Description: 8, 16, 32-bit WISHBONE Master // Supported cycles: MASTER, READ/WRITE // MASTER, BLOCK READ/WRITE // MASTER, RMW // Data port, size: 8, 16, 32-bit // Data port, granularity 8-bit // Data port, Max. operand size 32-bit // Data transfer ordering: little endian // Data transfer sequencing: undefined
Date : 2025-12-24 Size : 8kb User : 姓名
[VHDL-FPGA-Verilog] sequence_inspector DL : 0: 序列检测器可用于检测一组或多组二进制码组成的脉冲序列信号，这在数字通信领域中有广泛的应用。当序列检测器连续收到一组二进制码后，如果这组码与检测器中预先设置的码相同，则输出1，否则输出0。由于这种检测的关键在于正确码的收到必须是连续的，这就要求检测器必须记住前一次的正确码及正确序列，直到连续的检测中收到每一位都与预置数的对应码相同。在检测过程中，任何一位不相等都将回到初始状态重新开始检测。并附有测试程序-Sequence detector can be used to detect one or a binary code consisting of pulse sequence signal, which in the field of digital communications in a wide range of applications. When the sequence detector row received a group of binary code, if this group of codes and detectors in the same pre-set code, then output 1, otherwise output 0. As a result of this test lies in the receipt of the correct code must be continuous, which requires detector must be remembered that the previous code and correct the correct sequence, until the continuous detection and received every preset number of correspond to the same code. In the detection process, any one of unequal status will be returned to the initial detection of a fresh start. With test procedures
Date : 2025-12-24 Size : 1kb User : zhaohongliang
[VHDL-FPGA-Verilog] milixingzhuangtaiji DL : 0: 米立型状态机的输出变化要提前一个周期，即一旦输入信号或状态发生变化，输出信号立刻发生变化。-M-li-type state machine to advance the output changes in a cycle, that is, once the input signal or status change, the output signal of immediate change.
Date : 2025-12-24 Size : 1kb User : 孙超
[VHDL-FPGA-Verilog] qiangdaqi DL : 1: 用verilog编写的抢答器，当主持人宣布“开始比赛”，系统初始化，选手进入“抢答状态”。当某一选手首先按下抢答开关时，相应的指示灯亮，此时抢答器不再接受其他输入信号。电路具有累计分控制（分别用４个４位选手的积分——十六进制数），由主持人控制“加分”。“加分”加分完毕，开始下一轮抢答。电路还可以设有回答问题时间控制。 -Answer using Verilog prepared, and when the host announced the " start game" , the system initialization, players enter the " Answer status." When a player first of all, press the Answer the switch, the corresponding indicator light, when the Answer Explorer no longer accept other input signals. Circuit with a total of sub-control (separately with four players four points- hexadecimal number), by the host control " points." " Add points" add hours after beginning the next round of Answer. Circuit can also be equipped with time control to answer questions.
Date : 2025-12-24 Size : 1.05mb User : 叶
[VHDL-FPGA-Verilog] lcd_ddram DL : 0: 用于控制12832LCD文字显示的源程序，基于状态机制方法统编写的-12832LCD used to control the source text, based on the method of integration mechanisms for the preparation of status of
Date : 2025-12-24 Size : 1kb User : lzh
[VHDL-FPGA-Verilog] esm DL : 0: 详细介绍了三种高效状态机设计，其中还有PDF格式的说明（英文版）。-Detailed information on the status of the three high-performance design, including description of PDF format (in English).
Date : 2025-12-24 Size : 661kb User : 高峰亭
[VHDL-FPGA-Verilog] lift DL : 0: （1）用VHDL实现四层电梯运行控制器。（2）电梯运行锁用一按钮代替（开锁上电），低电平可以运行，高电平不能运行。（3）每层电梯入口处设有上行、下行请求按钮，电梯内设有乘客到达层次的停站要求开关，高电平有效。（4）有电梯所处楼层指示灯和电梯上行、下行状态指示灯。（5）电梯到达某一层时，该层指示灯亮，并一直保持到电梯到达另一层为止。电梯上行或下行时，相应状态指示灯亮。（6）电梯接收到停站请求后，每层运行2秒，到达停站层，停留2秒后门自动打开，开门指示灯亮，开门6秒后电梯自动关门。（7）能记忆电梯内、外的请求信号，并按照电梯的运行规则依次响应，请求信号保留至响应后撤除。（8）人数超载或超重用一按钮代替，高电平有效，超载时电梯不能运行，并有相应指示。（9）事故报警按钮高电平有效，事故报警不能运行，并有指示灯，信号保留至事故消除 -(1) the realization of four-storey elevator with VHDL controller operation. (2) elevator button with a lock to run in place of (unlock power), low run, can not run high. (3) on each floor with elevator at the entrance to the uplink, downlink request button, which are equipped with passenger elevators to reach the level of the requirements of stoppings switch, high effective. (4) elevators and escalators which lights up the floor, down the state indicator. (5) elevator to reach a certain level, the level indicator light, and has remained until the elevator arrived at another level. Elevator uplink or downlink, the corresponding status indicator light. (6) Elevator stops receiving a request, each running two seconds to reach the stops layer, two seconds back door stay open automatically, open the door indicator light, 6 seconds after the elevator door closed automatically. (7) to memory elevator inside and outside the request signal, and in accordance with the rules followed
Date : 2025-12-24 Size : 283kb User : 管皮皮
[VHDL-FPGA-Verilog] moore1 DL : 0: 根据潘松编著的教材编写的时序进程和状态进程分开的moore状态机-According to Pan Song of the materials for the timing process and the status of the process separate from the moore state machine
Date : 2025-12-24 Size : 295kb User : xuhongteng
[VHDL-FPGA-Verilog] example2 DL : 0: 状态机一般分为三种类型： Moore 型状态机：次态=f(现状，输入)，输出=f （现状）； Mealy 型状态机：次态=f(现状，输入)，输出=f （现状，输入）；混合型状态机。 -State machine is generally divided into three types: Moore-type state machine: sub-state = f (the status quo, input), output = f (status) Mealy type state machine: sub-state = f (the status quo, input), output = f ( the status quo, input) mixed state machine.
Date : 2025-12-24 Size : 25kb User : 汤化锋
[VHDL-FPGA-Verilog] example2 DL : 0: moore状态机程序一共有四个状况，空闲 idle 等待 ready 信号准备好后进入判决状态 decision 否则继续等待 ready信号；判决状态 decision 中将 oe、we 信号置低，同时根据read_write 判定下一个状态是读状态 read 还是写状态 write；如果 read_write 为‘1’读状态 read，否则写状态write；读状态将oe 置高，we 置低；写状态将 oe 置低，we 置高。-moore state machine processes a total of four conditions, idle idle wait for ready signal ready to enter the state decision or sentence to wait for ready signal ruling the state decision will oe, we set the signal low, but also with read_write to determine the next state is read- read, or write state write if read_write as ' 1 ' read-read, or write state write read status will oe set high, we set low write status will oe set low, we set high.
Date : 2025-12-24 Size : 31kb User : panda
[VHDL-FPGA-Verilog] clocktest.vhdl DL : 0: 时钟测试，vhdl，四位状态灯的转换，有复位信号-Clock test, vhdl, four status lights conversion, there are reset signal
Date : 2025-12-24 Size : 1kb User : 李维
[VHDL-FPGA-Verilog] LPC2DDR2 DL : 0: Module Function Description: This module allows a SPI ROM to be used in a LX/CS5536 system. Details are below: 1.Provide a memory window to the SPI EPROM at FFF80000h-FFFFFFFFh (512KB). 2.Provide an interface to the SPI bus to allow the SPI EPROM to be programmed. 3.Support DDR2 memory initial process. 4.Support LPC/SPI ROM switch using Hardware pin selection and Software setting method 5.Support LPC Memory Read/Write, LPC I/O Read/Write 6.Support SPI Chip Erase/Byte Program/Write Status/Read Status/Read Array -Module Function Description: This module allows a SPI ROM to be used in a LX/CS5536 system. Details are below: 1.Provide a memory window to the SPI EPROM at FFF80000h-FFFFFFFFh (512KB). 2.Provide an interface to the SPI bus to allow the SPI EPROM to be programmed. 3.Support DDR2 memory initial process. 4.Support LPC/SPI ROM switch using Hardware pin selection and Software setting method 5.Support LPC Memory Read/Write, LPC I/O Read/Write 6.Support SPI Chip Erase/Byte Program/Write Status/Read Status/Read Array
Date : 2025-12-24 Size : 8kb User : 吴羽中
[VHDL-FPGA-Verilog] dianti DL : 0: 1.每层电梯入口处设有上下请求开关各1个，电梯内设有乘客到达层次的数字开关。电梯当前所在的楼层位置用一位数码管显示，用一只发光二极管显示开门/关门状态，用发光二极管显示每层的上下请求状态； 2.显示电梯当前所处位置和电梯上行下行及开门，关门状态； 3.电梯到达有停靠站请求的楼层后，电梯门就会自动打开门指示灯亮，开门3秒钟后； 4.电梯门自动关闭（开门指示灯灭）电梯继续运行； 5.对电梯开门时间可以提前关门（按关门按钮）； 6.能记忆电梯内外的所有请求信号，并按照电梯运行的规则次第响应，每个请求信号保留至执行后撤除，如到达某层后，上下方均无请求，则电梯停在该层，中止运行。 -1. On each floor with elevator entrance and down a request for switching each one, equipped with passenger elevators to reach levels of digital switch. Lift the current location of where the floor with a digital tube display, with a light-emitting diode display open/close status, with the light-emitting diode displays on each floor of the upper and lower status of your request 2. Shows the current location of elevators and escalators up and down the door, closed state 3. Elevator stops the request to reach a floor, the elevator door will automatically open the door indicator light, open the door three seconds later 4. Elevator door is automatically closed (open the door light eliminate) elevator continues to run 5. Right time can advance the lift door closed (by closing the button) 6. Be able to remember all the requests inside and outside the elevator signal, and in accordance with the rules of elevator sequential response to each request signal after the removal of
Date : 2025-12-24 Size : 2kb User : kxsh
[VHDL-FPGA-Verilog] FIFO DL : 0: 该FIFO应当提供用户读使能和写使能输入控制信号，并输出指示FIFO状态的非空和非满信号，FIFO的输入、输出数据使各自的数据总线：in_data和out_data。-The FIFO should be provided to enable users to read and write enable input control signal, and outputs instructions FIFO status signals of non-empty and non-full, FIFO input and output data to make their respective data bus: in_data and out_data.
Date : 2025-12-24 Size : 102kb User : terry
[VHDL-FPGA-Verilog] Reads-the-DIP-switch-status DL : 0: 读取拨码开关状态，用LED灯显示出来。读取操作使用MOVX指令从CPLD中读到拨码开关状态。-Reads the DIP switch status display with LED lights. Read operation using the MOVX instruction read from CPLD DIP switch state.
Date : 2025-12-24 Size : 208kb User : 麦飞
[VHDL-FPGA-Verilog] The-FPGA-Status-and-trends DL : 0: 分析了FPGA的产品现状与应用前景，与FPGA的发展趋势，有助于了解行业的发展前景-Status and prospects of FPGA products, and FPGA trends, helps to understand the industry s development prospects
Date : 2025-12-24 Size : 3.42mb User : 张雨

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