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[VHDL-FPGA-Verilog] verilog_risc DL : 0: RISC状态机由三个功能单元构成：处理器、控制器和存储器。 RISC状态机经优化可实现高效的流水线操作。 RISC 中的数据线为16位。在数据存储器中的0到15的位置放置16个随机数，求16个数的和，放在数据存储器的16、17的位置，高位在前对这16个数进行排序，从大到小放置在18到33的位置求出前16个数的平均数，放在34的位置基本指令有NOP, ADD, SUB, AND, RD, WR, BR,BC。因为采用16位指令，有扩充的余地。-RISC state machine consists of three functional modules: processor, controller and memory. RISC state machine can be realized by optimizing the efficient pipelining. RISC data in line 16. In the data memory in the 0-15 position placed 16 random numbers, and the number 16 and, on the data memory of the 16,17 position, the previous high of 16 the number of these sort, smallest place in the 18-33 position to derive the average number of the top 16, on the location of 34 basic instructions are NOP, ADD, SUB, AND, RD, WR, BR, BC. Because the use of 16-bit instructions, there is room for expansion.
Date : 2026-01-15 Size : 126kb User : lyn
[VHDL-FPGA-Verilog] MedFilter_VHDL DL : 0: 用VHDL实现了Matlab中MedFilt1函数3阶中值滤波。进行排序时没有用软件使用的排序法，而是通过简单的比较实现。-VHDL implementation using the Matlab function MedFilt1 of 3-order median filter. Sort of no use when the software used to sort the Law, but through a simple comparison of implementation.
Date : 2026-01-15 Size : 2kb User : mike.chen
[VHDL-FPGA-Verilog] DataSort DL : 0: FPGA内，通过Verilog语言，实现冒泡法数据排序。仅供参考！-FPGA, through the Verilog language, implementation data bubble sort method. For reference purposes only!
Date : 2026-01-15 Size : 5kb User : weishiji
[VHDL-FPGA-Verilog] geshihua DL : 0: 读取文件的数据,并且按照一定的栏位排序.-Read the data file, and in accordance with a certain sort column.
Date : 2026-01-15 Size : 3kb User : 李民治
[VHDL-FPGA-Verilog] bubblesort1024ram DL : 0: 快速冒泡排序基于FPGA实现，有测试文件以及设计图，实现1024*32位数序的多数排序，突破传统是的REG类型少数排序，利用RAM，针对RAM中的无序数的地址调换，达到排序目的，仅供学习交流-Rapid bubble sort based on FPGA, there are test documents and design drawings to achieve 1024* 32-digit sequence of the majority of sorting, breaking tradition is a REG types of minority sorting, the use of RAM, the disorder for the RAM address of the number of exchange, to sort purpose, only to learn the exchange of.
Date : 2026-01-15 Size : 5kb User : 柳泽明
[VHDL-FPGA-Verilog] sort4 DL : 0: 基于ISE的FPGA应用，用来实现4输入的冒泡排序。-A application of bubble sort based on ISE.
Date : 2026-01-15 Size : 279kb User : Liu Wei
[VHDL-FPGA-Verilog] PING DL : 0: 一个甲、乙双方参赛，裁判参与的乒乓球比赛游戏模拟机。用8个发光二极管排成一条直线，以中点为界，两边各代表参赛双方的位置，其中点亮的发光二极管代表“乒乓球”的当前位置，点亮的发光二极管依次由左向右或由右向左移动。当球运动到某方的最后一位时，参赛者应立即按下自己一方的按钮，即表示击球，若击中，则“球”向相反方向运动，若未击中，则对方得1分。设置自动计分电路，双方各用二位数码管来显示计分，每局11分。每人发2球，7局4胜制。自动几分并显示-A A, B both play, the referee in the table tennis game simulator. With 8 LEDs arranged in a straight line, the midpoint for the community, representatives of both sides of the position of participating parties, including light-emitting diodes for " table tennis" in the current location, followed by light-emitting diode, or from left to right moving from right to left. When the ball movement to a party the last one, the participant should immediately press the button on its side, that means the ball, if hit, the " ball" in the opposite direction, if not hit, the other was a points. Automatic scoring circuit, each side with two digital displays scoring 11 points per game. Each made 2 balls, 7 Council 4 match. Automatically sort and display
Date : 2026-01-15 Size : 2kb User :
[VHDL-FPGA-Verilog] HowToUseModelSim DL : 0: modelsim教程大全，几分相当翔实的modelsim学习材料针对不同版本的modelsim都有讲解-Sort of learning materials very informative modelsim
Date : 2026-01-15 Size : 8.18mb User : 王先
[VHDL-FPGA-Verilog] sort DL : 0: 這個是排序,它可以幫妳把妳像要的數值進行排序-This is the sort that can help you turn on your values to be sorted as
Date : 2026-01-15 Size : 1kb User : shiyuanlin
[VHDL-FPGA-Verilog] Example-4-16 DL : 0: 串并转换建模数据流串并转换的实现方法多种多样，根据数据的排序和数量的要求，可以选用移位寄存器、RAM等来实现。对于数据量比较小的设计来说，可以使用移位寄存器完成串并转换；对于排列顺序有规定的串并转换，可以用case语句判断实现；对于复杂的串并转换，还可以用状态机实现-Modeling serial data stream and convert the realization of string and convert many ways, sort and quantity of the data requirements, you can use shift registers, RAM, etc. to achieve. Smaller than the design for the data, it can be done using the serial shift register and converted there are provisions for the order of the string and convert, you can use case statements to determine achieved for complex string and conversion state machine can also be used to achieve
Date : 2026-01-15 Size : 17kb User : 林立
[VHDL-FPGA-Verilog] keilc-shiyan3 DL : 0: 单处机实验程序，实现数据统计及排序实验熟悉单片机的指令系统，了解程序设计基本方法1、排序用冒泡排序算法-One experimental program at the machine, data statistics and sort familiar to microcontroller instruction experiment to understand the basic method of 1 programming, sorting using bubble sort algorithm
Date : 2026-01-15 Size : 8kb User : lipxiong
[VHDL-FPGA-Verilog] TRABALHO4 DL : 0: It s a sort of problem about sincronous operation using vhdl em DE2. Another homework lesson.
Date : 2026-01-15 Size : 199kb User : Marcio
[VHDL-FPGA-Verilog] caideng-xulie DL : 0: 数字电路与逻辑设计实验编程，有彩灯实验和序列排序实验。-Digital circuits and logic programming design experiments, and experiments with lights experiments sort sequence.
Date : 2026-01-15 Size : 333kb User : sunnxbest
[VHDL-FPGA-Verilog] Modulator70 DL : 0: 个人参与的某国家工程并行排序MATLAB程序，用于FPGA的RTLAB仿真，使用Simulink工具生成HDL代码。测试可用。-Individuals involved in sort of a national engineering parallel MATLAB programs for the FPGA RTLAB simulation, using the Simulink tool to generate HDL code. Test available.
Date : 2026-01-15 Size : 1kb User : 张张
[VHDL-FPGA-Verilog] maopao DL : 0: 利用verilog实现的冒泡排序。能够用于排任何多个数据的次序。-Implementation of bubble sort using verilog. Can be used for any number of rows of data in order.
Date : 2026-01-15 Size : 197kb User : sue
[VHDL-FPGA-Verilog] verilog--maopao-paixu DL : 0: 用verilog实现的冒泡排序法，有testbench-Implemented using verilog bubble sort, there is testbench
Date : 2026-01-15 Size : 2kb User : 阿神
[VHDL-FPGA-Verilog] Chapter-1 DL : 0: Verilog数字系统设计教程(第2版)”这本书的思考题没有答案，要多做实验和仿真-• Source code of designs in chapters 1 to 8. • Chapter 8 designs include the SAYEH processor, its C Compiler, and its Sort program run files. • Several Designs, including SAYEH, that are programmed on Altera’s UP2 board are included in “Quartus UP2 Designs.zip” • The OVL directory has OVL library version 1.0 and its documentations • In the Software directory, the Altera directory contains Quartus II, related tools, and Altera device specifications. Please connect to www.altera.com and then click on “University Program” to obtain a license for Quartus II Web Edition. • In the Software directory, The MentorGraphics directory has the ModelSim-Altera simulation program. Please connect to www.altera.com and then click on “University Program” to obtain a license for ModelSim-Altera.
Date : 2026-01-15 Size : 2kb User : shixiaodong
[VHDL-FPGA-Verilog] Chapter-2 DL : 0: Verilog数字系统设计教程(第2版)”这本书的思考题没有答案，要多做实验和仿真-• Source code of designs in chapters 1 to 8. • Chapter 8 designs include the SAYEH processor, its C Compiler, and its Sort program run files. • Several Designs, including SAYEH, that are programmed on Altera’s UP2 board are included in “Quartus UP2 Designs.zip” • The OVL directory has OVL library version 1.0 and its documentations • In the Software directory, the Altera directory contains Quartus II, related tools, and Altera device specifications. Please connect to www.altera.com and then click on “University Program” to obtain a license for Quartus II Web Edition. • In the Software directory, The MentorGraphics directory has the ModelSim-Altera simulation program. Please connect to www.altera.com and then click on “University Program” to obtain a license for ModelSim-Altera.
Date : 2026-01-15 Size : 5kb User : shixiaodong
[VHDL-FPGA-Verilog] Chapter-3 DL : 0: Verilog数字系统设计教程(第2版)”这本书的思考题没有答案，要多做实验和仿真-• Source code of designs in chapters 1 to 8. • Chapter 8 designs include the SAYEH processor, its C Compiler, and its Sort program run files. • Several Designs, including SAYEH, that are programmed on Altera’s UP2 board are included in “Quartus UP2 Designs.zip” • The OVL directory has OVL library version 1.0 and its documentations • In the Software directory, the Altera directory contains Quartus II, related tools, and Altera device specifications. Please connect to www.altera.com and then click on “University Program” to obtain a license for Quartus II Web Edition. • In the Software directory, The MentorGraphics directory has the ModelSim-Altera simulation program. Please connect to www.altera.com and then click on “University Program” to obtain a license for ModelSim-Altera.
Date : 2026-01-15 Size : 4kb User : shixiaodong
[VHDL-FPGA-Verilog] Chapter-4 DL : 0: Verilog数字系统设计教程(第2版)”这本书的思考题没有答案，要多做实验和仿真-• Source code of designs in chapters 1 to 8. • Chapter 8 designs include the SAYEH processor, its C Compiler, and its Sort program run files. • Several Designs, including SAYEH, that are programmed on Altera’s UP2 board are included in “Quartus UP2 Designs.zip” • The OVL directory has OVL library version 1.0 and its documentations • In the Software directory, the Altera directory contains Quartus II, related tools, and Altera device specifications. Please connect to www.altera.com and then click on “University Program” to obtain a license for Quartus II Web Edition. • In the Software directory, The MentorGraphics directory has the ModelSim-Altera simulation program. Please connect to www.altera.com and then click on “University Program” to obtain a license for ModelSim-Altera.
Date : 2026-01-15 Size : 7kb User : shixiaodong

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