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[VHDL-FPGA-Verilog] cordic DL : 0: verilog源代码，用于软件无线电中，cordic函数-Verilog source code for software radio, cordic function
Date : 2025-12-27 Size : 2kb User : 史兵
[VHDL-FPGA-Verilog] verilog DL : 0: 本代码设计的是一个通讯系统软件无线电中变换比为5/4的分数倍抽取器，用Verilog编程首先实现4倍内插，再实现5倍抽取。-The code design is a software-defined radio communication system in transformation ratio 5/4 points times the extractor, using Verilog programming the first to achieve four times the interpolation, and then taken to achieve five-fold.
Date : 2025-12-27 Size : 4kb User : 张霄