Search - soft input

Search - soft input - List

[VHDL-FPGA-Verilog] ver-fir-coefficient DL : 0: vhdl source,ver-fir-coefficient,simulink of fir with soft ware input
Date : 2025-12-20 Size : 390kb User : heti
[VHDL-FPGA-Verilog] MAX-PLUSII-soft DL : 0: MAX+PLUSII软件是一个功能强大，容易使用的软件包，它可以以图形方式、文字输入方式（AHDL、VHDL和VERILOG）和波形方式输入设计文件，可以编译并形成各种能够下装到EPROM和各种ALTERA器件的文件，还可以进行仿真以检验设计的准确性，下面举例说明该软件的使用-MAX+ PLUSII software is a powerful, easy-to-use software package, which can graphically, text input methods (AHDL, VHDL and VERILOG) and waveform enter design documents can be compiled and form can be downloaded to a variety of EPROM and ALTERA documents a variety of devices can also be used for simulation to test the accuracy of the design, the following examples to illustrate the use of the software
Date : 2025-12-20 Size : 122kb User : 徐靖
[VHDL-FPGA-Verilog] calc_v2_s3eboard DL : 0: Simple calculator EDK design implemented on Digilent S3EBOARD using Microblaze soft-core CPU. Input: PS/2 keyboard, output: VGA monitor.
Date : 2025-12-20 Size : 2.82mb User : madcrow
[VHDL-FPGA-Verilog] RECURSIVEALGORITHMFOREFFICIENTMAPDECODING DL : 0: Early termination enables powering down parts of the soft-input soft-output (SISO) equalizer and decoder thereby saving power.
Date : 2025-12-20 Size : 102kb User : suresh
[VHDL-FPGA-Verilog] viterbi_soft DL : 0: 维特比译码器，调用IP核，软判决输入，开发平台Xilinx Spartan-6系列FPGA-viterbi decoder, using IP core resource, soft decision input,develop platform is Xilinx Spartan-6 series FPGA
Date : 2025-12-20 Size : 3kb User : 王沛霖