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[VHDL-FPGA-Verilog] uart_vhdl_xilinx DL : 0: xilinx的串口仿真程序-xilinx simulator programme of serial port
Date : 2025-12-20 Size : 9kb User : 赵兴涛
[VHDL-FPGA-Verilog] lightW DL : 0: 一個LCD燈的小程序。不是我寫的。我只負責了調試。適用在ACEXEP1K30QC208-3上。我跑了SIMULATOR，管腳連接標示了。我也下在電路板上試過了，沒有問題。要用到實驗板上的兄弟們把CLK1改到TESTOUT3或者0就好了。綫幫助新手，人人有責。-a small LCD lights procedures. I did not write. I am only responsible for the debugging. Apply in ACEXEP1K30QC208-3 on. I run a simulator, marking the connecting pin. I next tried in a circuit board, there is no problem. Experimental use of the board brothers put CLK1 TESTOUT3 changed to a chorus or 0. Newcomers line help is everyone's responsibility.
Date : 2025-12-20 Size : 231kb User : 鄧翀
[VHDL-FPGA-Verilog] ModelSim6c_SE_Cracker DL : 0: crack for ModelSim, a Verilog, VHDL and mixed VHDL / Verilog CAD simulator for FPGA, board and IC design.-crack for ModelSim, a Verilog. VHDL and mixed VHDL/Verilog simulator for CAD F PGA, board and IC design.
Date : 2025-12-20 Size : 286kb User : 陈亨利
[VHDL-FPGA-Verilog] Vhdl_Simulation_With_Modelsim DL : 0: Triscend supports the use of the Model Technology ModelSim logic simulator for VHDL simulation of designs implemented in the Configurable System Logic (CSL) portion of a Triscend device.
Date : 2025-12-20 Size : 51kb User : zhangyg
[VHDL-FPGA-Verilog] verilog DL : 0: 北大微电子学系于敦山老师的课件，介绍Verilog HDL、Cadence Verilog仿真器、可综合的Verilog HDL、设计举例、自动布局布线工具、Verilog的词汇约定等内容-Department of Microelectronics, Peking University in the teacher s courseware mts on Verilog HDL, Cadence Verilog simulator can be integrated Verilog HDL, design, for example, automatic placement and routing tools, Verilog, etc. terms agreed
Date : 2025-12-20 Size : 1.48mb User : 唐进
[VHDL-FPGA-Verilog] ModelSim_Tutorial_V5.4 DL : 0: 这是关于如何使用Mentor社的ModelSim软件的说明书。ModelSim是HDL simulator中最常用的一个。-This is the agency on how to use Mentor
Date : 2025-12-20 Size : 688kb User : 许京哲
[VHDL-FPGA-Verilog] ddc_sim DL : 0: Digital downconvertor simulator
Date : 2025-12-20 Size : 15kb User : majid
[VHDL-FPGA-Verilog] RS_Euclid_FPGA DL : 0: RS译码的Euclid算法及其FPGA实现，并通过仿真器的出结果，对于设计ＲＳ译码很有帮助-RS decoding Euclid algorithm and its FPGA implementation, and through the simulator results are helpful for the design of RS decoder
Date : 2025-12-20 Size : 51kb User : 番茄
[VHDL-FPGA-Verilog] traffic_control DL : 0: 软件开发环境：ISE 7.1i 仿真环境：ISE Simulator 1. 这个实例实现通过ISE Simulator工具实现一个具有两个方向共八个灯的交通灯控制器； 2. 工程在project文件夹中，双击traffic.ise文件打开工程； 3. 源文件在rtl文件夹中，traffic.v为设计文件，traffic_tb.tbw是仿真波形文件； 4. 打开工程后，在工程浏览器中选择traffic_tb.tbw，在Process View中双击“Simulation Behavioral Model”选项，进行行为仿真，即可得到仿真结果。-Software development environment: ISE 7.1i simulation environment: ISE Simulator1. Realize this instance through the ISE Simulator tool to achieve a total of eight lights in both directions of traffic lights controller 2. Works project folder, double-click traffic.ise Open the project document 3. rtl source file in the folder, traffic.v for design documents, traffic_tb.tbw is the simulation waveform files 4. to open a project, the project browser, select traffic_tb.tbw, in the Process View in the double hit
Date : 2025-12-20 Size : 243kb User : 李华
[VHDL-FPGA-Verilog] vcs_simulation_mannual(Edition2) DL : 0: VCS-verilog compiled simulator是synopsys公司的产品.其仿真速度相当快,而且支持多种调用方式.该文档是一个不错的使用指南.-VCS-verilog compiled simulator is the Synopsys company s products. Its simulation at a fairly rapid pace, and support multiple call mode. This document is a good guide.
Date : 2025-12-20 Size : 174kb User : morisun
[VHDL-FPGA-Verilog] verilog_slides DL : 0: What is Verilog? ➥ Verilog HDL is a Hardware Description Language (HDL) ➥ Verilog HDL allows describe designs at a high level of abstraction as well as the lower implementation levels ➥ Primary use of HDLs is the simulation of designs ➥ Verilog is a discrete event time simulator What is VeriWell? ➥ VeriWell is a comprehensive implementation of Verilog HDL-What is Verilog?
Date : 2025-12-20 Size : 14kb User : 小刚
[VHDL-FPGA-Verilog] ADC_INTERFACE DL : 0: it is a verilog code written for MAX1886 ADC interin modelsim simulator and it will synthesize in xinlix ise 8.2i.i have tested it om my kit. -it is a verilog code written for MAX1886 ADC interin modelsim simulator and it will synthesize in xinlix ise 8.2i.i have tested it om my kit.
Date : 2025-12-20 Size : 6kb User : yasir ateeq
[VHDL-FPGA-Verilog] FIFO DL : 0: it is a verilog code written for FIFO in modelsim simulator and it will synthesize in xinlix ise 8.2i.i have tested it om my kit.[i mae my own kit for spartan2 device].you can use this code in any DSP project in which data entry is required.-it is a verilog code written for FIFO in modelsim simulator and it will synthesize in xinlix ise 8.2i.i have tested it om my kit.[i mae my own kit for spartan2 device].you can use this code in any DSP project in which data entry is required.
Date : 2025-12-20 Size : 31kb User : yasir ateeq
[VHDL-FPGA-Verilog] FPGA_radar DL : 1: 优秀硕士论文，基于FPGA的雷达信号模拟器设计，对学FPGA的，特别是学雷达的同学有很好的参考价值-Outstanding master s thesis, based on radar signal simulator FPGA design, FPGA-on study, in particular the study of radar has a good reference Student Value
Date : 2025-12-20 Size : 732kb User : zhang
[VHDL-FPGA-Verilog] plj DL : 0: 这是一个基于可编程逻辑器件的程序，用来实现自动转换量程频率计控制器，该程序在可以再仿真器上仿真实现-This is a programmable logic device based on the procedures used to automatically convert the frequency range of the controller, the program can be in the simulation simulator
Date : 2025-12-20 Size : 172kb User : jyb
[VHDL-FPGA-Verilog] GPSA DL : 0: FPGA低成本GPS信号模拟器设计GPS signal simulator designed low-cost FPGA-GPS signal simulator designed low-cost FPGA
Date : 2025-12-20 Size : 319kb User : beat
[VHDL-FPGA-Verilog] vcs-fang-zheng-2 DL : 0: VCS-verilog compiled simulator是synopsys公司的产品.其仿真速度相当快,而且支持多种调用方式使用的步骤和modelsim类似,都要先做编译,在调用仿真.-VCS-verilog compiled simulator is synopsys company' s products. The simulation very fast, and supports multiple call mode use similar steps and modelsim, we must do first compiled, the call simulation.
Date : 2025-12-20 Size : 175kb User : liyucai
[VHDL-FPGA-Verilog] TMS320C6000-Instr-set-simulator DL : 0: TMS320C6000 Instruction set simulator.rar
Date : 2025-12-20 Size : 444kb User : roc
[VHDL-FPGA-Verilog] infrared-simulator DL : 0: 用VHDL语言实现红外线的模拟装置，内容相当完备，是学习的好帮手。-VHDL language with infrared simulator, is quite complete, is to learn a good helper.
Date : 2025-12-20 Size : 594kb User : jiangdan
[VHDL-FPGA-Verilog] Xilinx-ISE-Simulator-(ISim)-VHDL-Test-Bench-Tutor DL : 0: Xilinx ISE Simulator (ISim) VHDL Test Bench Tutorial
Date : 2025-12-20 Size : 333kb User : giau

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