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[VHDL-FPGA-Verilog] USB枚举 DL : 0: ALTERA　NIOS处理器实验，编程环境是QUARTUS，在NIOS SHELL下编译实现功能。实验USB接口-Altera NIOS processor experiments, programming environment is QUARTUS in NIOS SHELL compiler functionality. Experimental USB interface
Date : 2025-12-22 Size : 35kb User : xf
[VHDL-FPGA-Verilog] LCD显示实验 DL : 0: ALTERA NIOS处理器，用VHDL在QUARTUS下编写，用NIOS SHELL调试通过，实验LCD液晶显示-Altera NIOS processor, using VHDL in QUARTUS prepared with NIOS SHELL debug through experimental LCD
Date : 2025-12-22 Size : 35kb User : xf
[VHDL-FPGA-Verilog] SRAM@DMA实验 DL : 0: ALTERA NIOS处理器实验，QUARTUS下用VHDL编译成处理器，然后NIOS　SHELL下C 语言运行。实验SRAM和DMA调度-Altera NIOS processor experiments QUARTUS using VHDL compiler into processor, then NIOS SHELL C language runtime. Experimental SRAM and DMA Scheduling
Date : 2025-12-22 Size : 33kb User : xf
[VHDL-FPGA-Verilog] SPI接口音频Codec实验 DL : 0: ALTERA NIOS处理器，VHDL语言在QUARTUS编译通过，然后有C语言在NIOS SHELL下驱动，实验音频解码-Altera NIOS processor, the QUARTUS VHDL compiler, then the C language under NIOS SHELL-driven, experimental audio decoder
Date : 2025-12-22 Size : 34kb User : xf
[VHDL-FPGA-Verilog] vani_tut DL : 0: A total of 52 files showing examples of shell scripting for Cadence NCSIM simulator, multiple single module + testbench examples in verilog 1995/2001, a "Randomized Smoothing Networks" paper (doc)+ppt+verilog codes and test bench from my EE7700 Distributed Algorithms Project.-A total of 52 files showing examples of shell scripting for Cadence NCSIM simulator, multiple single module+ testbench examples in verilog 1995/2001, a "Randomized Smoothing Networks" paper (doc)+ppt+verilog codes and test bench from my EE7700 Distributed Algorithms Project.
Date : 2025-12-22 Size : 264kb User : Stephen Bishop
[VHDL-FPGA-Verilog] cpu86 DL : 0: CPU86 - Free VHDL CPU8088 IP core Copyright (C) 2005-2010 HT-LAB Quick run: 1) Open a DOSBox/Cygwin shell 2) Navigate to the web_cpu88/Modelsim directory. 3) Execute run.bat See website for more details. The CPU86 core is released under the GNU GPL license. For more information read the copying.txt file located in this directory.-CPU86 - Free VHDL CPU8088 IP core Copyright (C) 2005-2010 HT-LAB Quick run: 1) Open a DOSBox/Cygwin shell 2) Navigate to the web_cpu88/Modelsim directory. 3) Execute run.bat See website for more details. The CPU86 core is released under the GNU GPL license. For more information read the copying.txt file located in this directory.
Date : 2025-12-22 Size : 549kb User : Dhaval
[VHDL-FPGA-Verilog] A-Verilog-HDL-Test-Bench-Primer DL : 0: verilog testbench 编写入门，轻松教会编写测试代码-shell interpreter tutorial information, content, round and rich, from the basics
Date : 2025-12-22 Size : 56kb User : 赵玉祥
[VHDL-FPGA-Verilog] ddr_data_path DL : 0: sdram数据路径模块编程，经综合后壳生成rtl级电路图-SDRAM data path module shell programming, after comprehensive RTL-level circuit diagram is generated
Date : 2025-12-22 Size : 2kb User : xiaojie