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[VHDL-FPGA-Verilog] S3Demo DL : 0: Spartan 3 Digilent Demo:This demo drives the perphrials on the Spartan 3 board. This drives a simple pattern to the VGA port, connects the switches to the LEDs, buttons to each anode of the seven segment decoder. The seven segment decoder has a simple counter running on it, and when SW0 is in the up position the seven segment decoder will display scan codes from the PS2 port. This demo how ever does not drive the RS-232 port or the memory. This is a simple design done entirely VHDL not microblaze.
Date : 2026-01-10 Size : 714kb User : Roy Hsu
[VHDL-FPGA-Verilog] 7led DL : 0: 一个最大公约数七段显示器编码VHDL代码设计-Seven-Segment display a common denominator coding VHDL code design
Date : 2026-01-10 Size : 3kb User : linew
[VHDL-FPGA-Verilog] VHDLjindianshili DL : 0: 37个经典的VHDL程序。有比较器、七段译码器、状态机等。-37 classic VHDL procedures. Have comparators, Seven-Segment decoder, such as state machines.
Date : 2026-01-10 Size : 39kb User : kcamellia
[VHDL-FPGA-Verilog] work3CNT4BDECL7S DL : 0: 7段数码显示译码器设计7段数码是纯组合电路，通常的小规模专用IC，如74或4000系列的器件只能作十进制BCD码译码，然而数字系统中的数据处理和运算都是二进制的，所以输出表达都是十六进制的，为了满足十六进制数的译码显示，最方便的方法就是利用译码程序在FPGA/CPLD中来实现。例子作为七段译码器，输出信号LED7S的7位分别接数码管的7个段，高位在左，低位在右。例如当LED7S输出为“1101101”时，数码管的7个段g、f、e、d、c、b、a分别接1、1、0、1、1、0、1；接有高电平的段发亮，于是数码管显示“5”。-7 digital display decoder design 7 Digital is pure combinational circuits, usually of small-scale dedicated IC, such as 74 or 4000 Series devices can only be used to decimal BCD decoder, but digital systems in the data processing and computing are binary, so the output expression are hexadecimal, and hexadecimal number in order to meet the needs of the decoding shows that the most convenient way is to use decoding process in FPGA/CPLD in to achieve. Seven-Segment decoder as an example, the output signal of the seven were LED7S access digital pipe 7 above, high in the left, low in the right. For example, when LED7S output as
Date : 2026-01-10 Size : 81kb User : lkiwood
[VHDL-FPGA-Verilog] freqm DL : 0: a simple implementation of a frequency meter with the BCD-counter and the 7-segment LED display
Date : 2026-01-10 Size : 12kb User : wangfeng
[VHDL-FPGA-Verilog] 04_dynamic_hex2 DL : 0: This is 7-segment LED contoler in vhdl
Date : 2026-01-10 Size : 7kb User : darek
[VHDL-FPGA-Verilog] VerilogHDL_code DL : 0: 几个常用的接口实验的程序代码，用Verilog HDL语言编写的，包括七段数码管、拨码开关、蜂鸣器、矩阵键盘、串口、I2C、跑马灯等。-Some commonly used experimental procedures for the interface code, using Verilog HDL language, including Seven-Segment LED, DIP switch, buzzer, matrix keyboard, serial, I2C, marquees, etc..
Date : 2026-01-10 Size : 1.53mb User : shsh
[VHDL-FPGA-Verilog] 7-segment DL : 0: VHDL Design of BCD to 7-segment decoder using PROM
Date : 2026-01-10 Size : 59kb User : FATIMA
[VHDL-FPGA-Verilog] DE2 DL : 0: 使用 DE2板制作的多功能数字钟，含有选择功能，秒表，电子表，闹钟，用7-segment LED液晶显示，可以通过LCD看当时状态附有仿真波形--Clk_Div,- Mode_Select,-Watch,-stop_watch,-Lcd_Module,-Total_Out source code，Simulation waveform
Date : 2026-01-10 Size : 3.52mb User : 赵香君
[VHDL-FPGA-Verilog] rafal2 DL : 0: VHDL project for FPGA SPartan 3 using IseWebpack 10.1. This is an implemetation of FSM for testing 7 segment with dot point 4 digit LED display.
Date : 2026-01-10 Size : 919kb User : nukom
[VHDL-FPGA-Verilog] qiduan DL : 0: 用vhdl语言实现按键操控多个七段码控制-Vhdl language with control buttons to control a number of Seven-Segment Code
Date : 2026-01-10 Size : 139kb User : 邢旭
[VHDL-FPGA-Verilog] Mars-EP1C6-F_code2 DL : 0: 此包为FPGA学习板接口实验程序源代码,共包括13个实验程序,有7段数码管,1602液晶显示,12864液晶显示,I2C总线,串口通信,拨码开关等.-The packet interface to FPGA board experimental procedure to study the source code, a total of 13 experimental procedure, there are 7-segment digital tube, 1602 LCD 12864 LCD, I2C bus, serial communication, DIP switch.
Date : 2026-01-10 Size : 4.42mb User : sunxh092
[VHDL-FPGA-Verilog] display DL : 0: vhdl,七段数码管驱动程序，完成数字显示功能-vhdl, seven-segment digital tube driver, complete the digital display
Date : 2026-01-10 Size : 84kb User : 王晓虎
[VHDL-FPGA-Verilog] Seven-Segment-Decoder DL : 0: 用VHDL语言在FPGA上实现将十进制bcd码转换成七段led显示码-FPGA using VHDL language to achieve will be converted to decimal bcd yards led seven segment display code
Date : 2026-01-10 Size : 1kb User : 吴金通
[VHDL-FPGA-Verilog] verilog DL : 0: 通过I2C接口读写EEPROM 在本项目中，我们利用Verilog HDL实现了部分I2C总线功能，并能够通过该总线对AT24C02进行读写操作。为了便于观察读写eeprom的结果，我们将读写的数据同时显示在七段数码管上，并设定读写的数据从0到255不断循环，这样就可以方便进行比较。 -Through the I2C interface to read and write EEPROM in this project, we use Verilog HDL to achieve some of the I2C bus function, and can be carried out through the bus, read and write operations on the AT24C02. To read and write eeprom in order to facilitate observation of the results, we will read and write data simultaneously displayed in the seven-segment digital tube, and set read and write data from 0 to 255 in cycles, so that can be easily compared.
Date : 2026-01-10 Size : 8kb User : andy
[VHDL-FPGA-Verilog] digital_seven_segment_clock DL : 0: digital seven segment clock
Date : 2026-01-10 Size : 2kb User : Harry Sunaryo
[VHDL-FPGA-Verilog] Verilog_UDP DL : 0: 辛辛苦苦找到的UDP的资料，在verilog中UDP指的是用户定义的原语。比如说大家有时候会见到“primitive...table...endtable...endendprimitive”这样的代码段，在书上只能找到大概的解释。到网上查的话又老是跟TCP/IP的UDP冲突。所以特地搜集到了这个东西，希望能帮助大家解决“用户原语”相关的问题。-UDP hard to find the information in verilog in the UDP refers to the user-defined primitives. For example, we sometimes see the " primitive ... table ... endtable ... endendprimitive" This code segment can only be found in the book about interpretation. The online search, then they are always with the TCP/IP, UDP conflict. So, specifically to collect this stuff, hoping to help people solve the " user of the original language" related issues.
Date : 2026-01-10 Size : 123kb User : 龙也
[VHDL-FPGA-Verilog] xq_Test7 DL : 0: VHDL语言编写一个BCD计数器并在七段显示数码管上显示的程序,实现了动态扫描，而且很好用-VHDL language a BCD counter and in the seven-segment display digital tube display process to achieve a dynamic scanning, and it just works
Date : 2026-01-10 Size : 141kb User : 夏强
[VHDL-FPGA-Verilog] 7segmentLED DL : 0: 7段数码管显示源代码。基于VHDL语言，实现对7段数码管显示。-7 segment LED display source code. Based on the VHDL language, achieving seven segment LED display.
Date : 2026-01-10 Size : 3kb User : xiaokun
[VHDL-FPGA-Verilog] VHDL-3BCD DL : 0: 3位BCD码的计数显示电路。BCD码计数电路从0计到9然后返回到0从新计数。3位BCD码计数器可以实现从0到999的十进制计数。要将计数过程用七段显示LED数码管显示出来，这里采用动态分时总线切换电路对数码管进行扫描，对数码管依次分时选中进行输出计数的个、十、百位的数据。-3 BCD code count display circuit. BCD code counting circuit count from 0 to 9 and then back to 0 from the new count. 3 BCD code counter can be achieved from 0 to 999 decimal count. Counting process with seven segment displays to LED digital tube displays, where dynamic time-sharing digital bus switch circuit to scan, followed by time-sharing of digital output selected for a count of ten, hundred bits of data.
Date : 2026-01-10 Size : 55kb User : will li

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