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[VHDL-FPGA-Verilog] 2Dfft DL : 0: VHDL 关于2DFFT设计程序 u scinode1 ∼ scinode9.vhd: Every SCI node RTL vhdl code. The details can be seen in the following section. u 2dfft.vhd: The top module includes these scinodes and form a 3x3 SCI Torus network, and it support these sub-modules scinode1∼ scinode9 reset and clk and global_cnt signals to synchronous the sub-modules to simplify the overall design. u proj2.wfc: VSS simulation result that is the same as the ModelSim simulation result. u Pro2_2.wfc: VSS simulation result of another test pattern can’t cause overflow situation.-VHDL design procedures on 2DFFT u scinode1
Date : 2025-12-14 Size : 765kb User : 李成
[VHDL-FPGA-Verilog] uartverlog DL : 0: 占用资源少的verilog HDL uart接口；采用固定波特率115200，可以修改程序中的分频来修改波特率，模式为1个启始位，8位数据位，1个停止位；带1字节缓存；当缓存空时输出空信号-Occupy fewer resources verilog HDL uart interface adopted a fixed baud rate of 115200, can modify the procedure to modify the baud rate frequency, the model of a start bit, 8 data bits, 1 stop bit with one word section of the cache when the cache empty space-time output signal
Date : 2025-12-14 Size : 2kb User : 张诚
[VHDL-FPGA-Verilog] uart_VHDL DL : 0: UART的一段VHDL程序，可以作为参考-UART section of VHDL procedures, can be used as reference
Date : 2025-12-14 Size : 10kb User : wangwei
[VHDL-FPGA-Verilog] cpld DL : 0: 基于CPLD XC95018开发的一段VHDL代码，可实现多个8051单片机互相通讯，对多单片机系统的设计很有参考价值-Based on CPLD XC95018 developed section of VHDL code, can realize more than 8051 mutual communication, single-chip microcomputer system for the design of multi-reference value is
Date : 2025-12-14 Size : 886kb User : 蔡彬彬
[VHDL-FPGA-Verilog] 100vhdl_example DL : 0: vhdl语言的100个例子 VHDL语言100例第1例带控制端口的加法器第2例无控制端口的加法器第3例乘法器第4例比较器第5例二路选择器第6例寄存器第7例移位寄存器第8例综合单元库第9例七值逻辑与基本数据类型第10例函数 -VHDL language, VHDL language 100 examples of 100 cases of the first one cases of the control port with the first two cases of adder uncontrolled port adder section 3 cases of the first four cases of multiplier comparator section Selector Rd 5 cases of the first six cases of the first register 7 cases of the first eight cases of shift register integrated cell library the first nine cases of the seven-valued logic and basic data types the first 10 cases of function
Date : 2025-12-14 Size : 218kb User : 光明顶
[VHDL-FPGA-Verilog] vhdl DL : 0: 自己弄的一小段程序代码，给大家看看，望多给点意见。-Get their own small section of program code, for everyone to see, hope more points.
Date : 2025-12-14 Size : 2kb User : 胡懿君
[VHDL-FPGA-Verilog] usb_phy.tar DL : 0: Very simple USB 1.1 PHY. Includes all the goodies: serial/parallel conversion, bit stuffing/unstuffing, NRZI encoding decoding. Uses a simplified UTMI interface. Currently doesn t do any error checking in the RX section [should probably check for bit unstuffing errors]. Otherwise complete and fully functional. There is currently no test bench available. This core is very simple and is proven in hardware. I see no point of writing a test bench at this time.
Date : 2025-12-14 Size : 7kb User : eldis
[VHDL-FPGA-Verilog] yejing DL : 0: 一段基于VHDL的液晶显示程序，和大家分享！-Section of the liquid crystal display based on the VHDL program, and everyone to share!
Date : 2025-12-14 Size : 1kb User : 葛宪生
[VHDL-FPGA-Verilog] LEDVHDL DL : 0: 8.2 LED控制VHDL程序与仿真本节分别介绍采用FPGA对LED进行静态和动态显示的数字时钟控制程序。 1. 例1：FPGA驱动LED静态显示 --文件名：decoder.vhd。 --功能：译码输出模块，LED为共阳接法。 --最后修改日期：2004.3.24。 -8.2 LED control and simulation of VHDL procedures introduced in this section of the LED using FPGA static and dynamic display of digital clock control procedures. 1. Cases 1: FPGA-driven static LED display- File name: decoder.vhd.- Function: Decoding output module, LED connection for a total of Yang.- Last modified date: 2004.3.24.
Date : 2025-12-14 Size : 5kb User : wangnan
[VHDL-FPGA-Verilog] choosebcd DL : 0: 48位BCD码自动识别，并判断是否有无用位，并输出到下一段输出-48 BCD code automatic identification and to determine whether any use of digital and output to the next section of the output
Date : 2025-12-14 Size : 1kb User : hao
[VHDL-FPGA-Verilog] final_5 DL : 0: 5. 對於按鍵輸入密碼鎖，假設reset後，七節燈管顯示「0」，而且使用sw1、sw2二個，那麼sw2-> sw1-> sw1-> sw2時，表示正確開鎖，會令七節燈管顯示「8」。-5. For the key to enter a password lock, assuming that reset after the seven lamp displays " 0" , and the use of sw1, sw2 two, then sw2-> sw1-> sw1-> sw2, it said that unlocking the right will lead to 7 Section lamp display " 8."
Date : 2025-12-14 Size : 634kb User : samaria
[VHDL-FPGA-Verilog] oc_i2c_master DL : 0: I 2 C 是两线双向的串行接口，非常适合芯片级的通讯。由于 SOPC Builder并未提供 I 2 C 内核，本节所描述的 I 2 C 内核是 Richard Herveille 制作的并发布到网上去的免费核。关于 I 2 C 核的使用方法，请见光盘中 oc_i2c_master文件夹下的使用说明.txt。 -I 2 C is a 2-line bidirectional serial interface, very suitable for chip-level communication. Because SOPC Builder does not provide I 2 C core, as described in this section I 2 C core is produced by Richard Herveille and publish to the web free of charge to go nuclear. With regard to I 2 C core to use, see the CD-ROM folder oc_i2c_master use instructions. Txt.
Date : 2025-12-14 Size : 254kb User : xuai
[VHDL-FPGA-Verilog] display DL : 0: 在spartan3e开发板的数码管部分显示数字-Spartan3e development board in the digital control section shows the number
Date : 2025-12-14 Size : 6kb User : 长江
[VHDL-FPGA-Verilog] BCD DL : 0: BCD\七段显示译码器数码管段显示发光二级管是共阴连结，所以显示高电平有效，即哪一段的驱动信号为高电平，则对应段发亮-BCD \ seven-segment display decoder digital tube sections show light-emitting diode is a link to a total of yin, it showed high and effective, that is what section of the drive signal is high, then the corresponding segment bright
Date : 2025-12-14 Size : 17kb User : bryan
[VHDL-FPGA-Verilog] display_with_dia DL : 0: 本实验仪提供了6 位8段码LED显示电路，学生只要按地址输出相应数据，就可以实现对显示器的控制。显示共有6位，用动态方式显示。8位段码、6位位码是由两片74LS374输出。位码经MC1413或ULN2003倒相驱动后，选择相应显示位。本实验仪中 8位段码输出地址为0X004H，位码输出地址为0X002H。此处X是由KEY/LED CS 决定，参见地址译码。做键盘和LED实验时，需将KEY/LED CS 接到相应的地址译码上。以便用相应的地址来访问。例如，将KEY/LED CS接到CS0上，则段码地址为08004H，位码地址为08002H。 -This experimental device provides six LED display circuit 8 code, students will address output by the corresponding data can be achieved on the control display. Shows a total of 6, with the dynamically displayed. 8-bit code segment, 6-bit code output by two 74LS374. Bit code by the MC1413 or ULN2003 inverter drive, select the appropriate display position. The experimental device in 8-bit code segment output address 0X004H, bit code output address 0X002H. Where X is the KEY/LED CS decision, see the address decoding. Do keyboard and LED experiment, take the KEY/LED CS on receiving the appropriate address decoding. In order to use the appropriate address to access. For example, KEY/LED CS received CS0 on the section of code address is 08004H, bit code address is 08002H.
Date : 2025-12-14 Size : 134kb User : yangxiao
[VHDL-FPGA-Verilog] LAB26 DL : 0: EDA基础_综合实验篇__实验二十六 VGA显示器彩条信号发生器-EDA based on comprehensive test papers _ __ experiment 26 color VGA monitor signal generator section
Date : 2025-12-14 Size : 313kb User : wonder
[VHDL-FPGA-Verilog] vga_disp DL : 0: 本程序为自己毕业设计用，可通过数据控制VGA显示动态竖彩条，为了使大家容易理解此程序，我对其中关键处作了详细说明，希望对FPGA爱好者和FPGA初学者有用!-The graduate program designed for their own use, data control via dynamic vertical color VGA display section, in order for you easy to understand this process, key Department of which I explained in detail, I hope fans of the FPGA be useful!
Date : 2025-12-14 Size : 1kb User : 常娟成
[VHDL-FPGA-Verilog] vga DL : 0: 用VHDL实现VGA显示,在VGA显示器上显示彩色条，用的FPGA是Lattice公司的XP2-5.程序测试通过，附图片资料-VHDL implementation with VGA display, the VGA color monitor display section, with the FPGA, Lattice' s XP2-5. Procedures tested, with a picture information
Date : 2025-12-14 Size : 700kb User :
[VHDL-FPGA-Verilog] VHDL DL : 0: 1.7段数码译码器 2.4人表决器 3.8421码十进制计数器 4.9秒减计数器-1.7 Section 2.4 digital decoder person voting 3.8421 yards in 4.9 seconds by a decimal counter counter
Date : 2025-12-14 Size : 8kb User : 99
[VHDL-FPGA-Verilog] sdh1 DL : 0: 本段代码是关于SDH帧的操作的一段VHDL的代码。主要需求为两部分： 1. 从连续传输的SDH字节流中找出帧头。 2. 从SDH字节流中，提取F1字节，并按照要求输出。-This section of code is on the operation of a SDH frame VHDL code. Two main needs: 1. From the continuous transmission of SDH byte stream to find the frame header. 2. SDH bytes from the stream, extract F1 bytes and the requested output.
Date : 2025-12-14 Size : 1kb User : mao

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