Search - scheduling algorithm

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[VHDL-FPGA-Verilog] mux DL : 0: 多路选择器是一个多输入，单输出的组合逻辑电路，在算法电路的实现中常用来根据地址码来调度数据。-MUX is a multi-input, single-output combinational logic circuit, in the algorithm used in the realization of circuits to address code in accordance with scheduling data.
Date : 2025-12-26 Size : 117kb User : 张应辉
[VHDL-FPGA-Verilog] os2 DL : 0: FIFO优先权调度算法实现。能够实现页的调入与调出。-FIFO priority scheduling algorithm. Transferred to the page can be achieved with the recall.
Date : 2025-12-26 Size : 2kb User : 陈燕
[VHDL-FPGA-Verilog] a DL : 0: 模拟先进先出（FIFO）页面调度算法处理缺页中断-Analog FIFO (FIFO) scheduling algorithm page page fault handling
Date : 2025-12-26 Size : 1kb User : 阿迷
[VHDL-FPGA-Verilog] fifo DL : 0: 模拟页式虚拟存储管理中硬件的地址转换和用先进先出调度算法处理缺页中断.虽然是文档文件，其源代码可以直接拷贝至C++运行，并且文档最后给出相应执行结果。-Simulation of the hardware address translation page of virtual storage management and FIFO scheduling algorithm for processing a page fault, although it is a document file and its source code can be directly copied to the C++ run, and the end of the document gives the corresponding results of the implementation.
Date : 2025-12-26 Size : 57kb User : hwq
[VHDL-FPGA-Verilog] rc4 DL : 0: RC4 is the most popular stream cipher in the domain of cryptology. RC4 consist of two algorithms Key Scheduling Algorithm (KSA) and Pseudo-random generation algorithm (PRGA).
Date : 2025-12-26 Size : 48kb User : varalakshmi