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[VHDL-FPGA-Verilog] SRAM@DMA实验 DL : 0: ALTERA NIOS处理器实验，QUARTUS下用VHDL编译成处理器，然后NIOS　SHELL下C 语言运行。实验SRAM和DMA调度-Altera NIOS processor experiments QUARTUS using VHDL compiler into processor, then NIOS SHELL C language runtime. Experimental SRAM and DMA Scheduling
Date : 2026-01-11 Size : 33kb User : xf
[VHDL-FPGA-Verilog] elivator_control DL : 0: 电梯控制器用于八层楼双电梯的协调调度可进行扩展-Elevator controller for the eight-floor, two-elevator scheduling coordination can be extended
Date : 2026-01-11 Size : 532kb User : 王鹤
[VHDL-FPGA-Verilog] combine_module DL : 0: 本代码根据包头、包尾指示，将两路数据合路调度成一路输出-The code according to Baotou, including the end of the instructions will be two-way data path scheduling together all the way into the output
Date : 2026-01-11 Size : 2kb User : yang
[VHDL-FPGA-Verilog] elock.verilog.pdf DL : 0: 一种基于Verilog的电子密码锁的论文介绍。有部分程序代码。-Verilog-based electronic locks thesis introduction. Some program code.
Date : 2026-01-11 Size : 288kb User : 李里
[VHDL-FPGA-Verilog] mux DL : 0: 多路选择器是一个多输入，单输出的组合逻辑电路，在算法电路的实现中常用来根据地址码来调度数据。-MUX is a multi-input, single-output combinational logic circuit, in the algorithm used in the realization of circuits to address code in accordance with scheduling data.
Date : 2026-01-11 Size : 117kb User : 张应辉
[VHDL-FPGA-Verilog] os2 DL : 0: FIFO优先权调度算法实现。能够实现页的调入与调出。-FIFO priority scheduling algorithm. Transferred to the page can be achieved with the recall.
Date : 2026-01-11 Size : 2kb User : 陈燕
[VHDL-FPGA-Verilog] all_cpu_scheduling DL : 0: the program gives cpu scheduling implementation
Date : 2026-01-11 Size : 1kb User : neeraj
[VHDL-FPGA-Verilog] a DL : 0: 模拟先进先出（FIFO）页面调度算法处理缺页中断-Analog FIFO (FIFO) scheduling algorithm page page fault handling
Date : 2026-01-11 Size : 1kb User : 阿迷
[VHDL-FPGA-Verilog] paixu DL : 0: 给定一个带期限的作业排序问题, n=5, (p1,p2,p3,p4,p5)=(6,3,4,8,5), (t1,t2,t3,t4,t5)=(2,1,2,1,1), (d1,d2,d3,d4,d5)= (3,1,4,2,4), 应用FIFOBB求使总罚款数最小的可行作业集J, 要求:实现对不同作业排序问题实例的求解，问题实例的输入数据存储在case.txt文件中。-Given a scheduling problem with the operation period, n = 5, (p1, p2, p3, p4, p5) = (6,3,4,8,5), (t1, t2, t3, t4, t5) = (2,1,2,1,1), (d1, d2, d3, d4, d5) = (3,1,4,2,4), seeking to make a total fine of application FIFOBB the smallest possible number of job set J, requirements: to achieve the scheduling problem instances of different operating solving the problem instance of the input data is stored in the case.txt file。
Date : 2026-01-11 Size : 2kb User : zhoukejian
[VHDL-FPGA-Verilog] singlecpu DL : 0: 模拟单时钟CPU，可实现add,sub,and,or,nor等多条指令。包括CPU调度、加法器、PC计数器完整的数据通道。-Analog single-clock CPU, can achieve the add, sub, and, or, nor so many instructions. Including CPU scheduling, adder, PC counter complete data channel.
Date : 2026-01-11 Size : 66kb User : Liao Jinxing
[VHDL-FPGA-Verilog] abbr_564dd181 DL : 0: 数据采集和控制系统多种多样，但其基本工作过程相似：汇集被测控对象各种被测模拟量，把它们转换为数字信号，经过加工处理后，再转换成相应的模拟量，实现所需的控制。上述过程由数据采集控制器统一管理和调度。-Data acquisition and control systems are diverse, but similar to the basic work process: collection of various objects being tested analog measurement and control, convert them to digital signals, after processing, the converted to the corresponding analog, to achieve the required of control. The process from data acquisition controller unified management and scheduling.
Date : 2026-01-11 Size : 27kb User : 李佳悦
[VHDL-FPGA-Verilog] fifo DL : 0: 模拟页式虚拟存储管理中硬件的地址转换和用先进先出调度算法处理缺页中断.虽然是文档文件，其源代码可以直接拷贝至C++运行，并且文档最后给出相应执行结果。-Simulation of the hardware address translation page of virtual storage management and FIFO scheduling algorithm for processing a page fault, although it is a document file and its source code can be directly copied to the C++ run, and the end of the document gives the corresponding results of the implementation.
Date : 2026-01-11 Size : 57kb User : hwq
[VHDL-FPGA-Verilog] cunchuguanli DL : 0: 模拟请求页式存储管理中硬件的地址转换和缺页中断，并用先进先出调度算法（FIFO）处理缺页中断；-Simulation request page storage management hardware address translation and page fault interrupt and FIFO scheduling algorithms (FIFO) processing a page fault
Date : 2026-01-11 Size : 2kb User : 菲菲
[VHDL-FPGA-Verilog] SP_SCH(Executable) DL : 0: 调度器一般包括SP、RR、WFQ等，SP调度指的是绝对高优先级调度，此种调度不带权重概念，按照优先级进行调度。四个按键作为端口有效指示，2个LED发光二极管指示此时调度的端口号，可以按下KEY3按键，按下按键代表当前按键输入无效，然后观测LED，没有按下的时候LED1 LED0都发光，按下KEY3按键的时候LED1发光 LED0不发光，代表此时调度端口为2，不按下时候代表调度端口为3。 -The scheduler typically include SP, RR, WFQ, etc., SP scheduling refers to the absolute high-priority scheduling, dispatching without the weight of such concepts, in accordance with the priority scheduling. Four buttons as a port and effective instruction, the port number 2 LED LED indication at this time schedule, you can press KEY3 button, press the button that represents the current key input is invalid, then the observed LED, LED1 LED0 not pressed when all light, when the button is pressed KEY3 luminous LED0 LED1 does not light, this time on behalf of the scheduling port 2, do not press on behalf of scheduling when the port is 3.
Date : 2026-01-11 Size : 6.49mb User : wangfeng
[VHDL-FPGA-Verilog] RR_SCH(Executable) DL : 0: FPGA VERILOG调度器一般包括SP、RR、WRR、WFQ等，RR调度指的是轮询调度，此种调度不带权重概念，均匀轮询进行调度。-FPGA VERILOG The scheduler typically include SP, RR, WRR, WFQ, etc., RR refers to the round robin scheduling, dispatching without the weight of such concepts, even polling scheduling.
Date : 2026-01-11 Size : 3.52mb User : 网窝囊
[VHDL-FPGA-Verilog] sch DL : 0: 电子系统设计高层次综合high level synthesis 源码,C++ 实现调度-electronic system level HLS design, cpp code for scheduling
Date : 2026-01-11 Size : 2kb User : wang bo
[VHDL-FPGA-Verilog] rc4 DL : 0: RC4 is the most popular stream cipher in the domain of cryptology. RC4 consist of two algorithms Key Scheduling Algorithm (KSA) and Pseudo-random generation algorithm (PRGA).
Date : 2026-01-11 Size : 48kb User : varalakshmi