Search - rs-232

Search - rs-232 - List

[VHDL-FPGA-Verilog] 结合XILINXCPLD RS232通信(verilog) DL : 0: 结合XILINXCPLD所做的模拟RS232通信verilog源程序-XILINXCPLD combine the simulation RS232 communication Verilog source
Date : 2026-01-01 Size : 119kb User : 于飞
[VHDL-FPGA-Verilog] RS232-for-vdhl DL : 0: RS232通讯VHDL源代码,MAXPLUS 2环境执行通过-RS232 communications VHDL source code, Segments 2 environment through implementation
Date : 2026-01-01 Size : 158kb User : lq
[VHDL-FPGA-Verilog] USBXilinx DL : 0: 实现了串行通信接口的全部功能，符合RS-232-C标准的完整UART模块源代码，中文注解，清晰易懂，经过严格仿真测试，绝对好用。-a serial communication interface of all functions, with RS-232-C standard UART modules complete source code, Chinese notes, lucid, after a rigorous simulation tests, absolutely useful.
Date : 2026-01-01 Size : 452kb User : 张海
[VHDL-FPGA-Verilog] S3Demo DL : 0: Spartan 3 Digilent Demo:This demo drives the perphrials on the Spartan 3 board. This drives a simple pattern to the VGA port, connects the switches to the LEDs, buttons to each anode of the seven segment decoder. The seven segment decoder has a simple counter running on it, and when SW0 is in the up position the seven segment decoder will display scan codes from the PS2 port. This demo how ever does not drive the RS-232 port or the memory. This is a simple design done entirely VHDL not microblaze.
Date : 2026-01-01 Size : 714kb User : Roy Hsu
[VHDL-FPGA-Verilog] Chapter5Sample DL : 0: 主要是RS-232串行接口技术并且通过了串行收发器UART的开发实例演示了接口设计的基本步骤程序-Is RS-232 serial interface technology and, through a serial UART transceiver development of interface design examples demonstrate the basic steps of the procedure
Date : 2026-01-01 Size : 22kb User : 玄冰
[VHDL-FPGA-Verilog] S7_PS2_RS232 DL : 0: 本实验实现PS/2接口与RS-232接口的数据传输， PS/2键盘上按下按键，可以通过RS-232自动传送到主机的串口调试终端上（sscom32.exe）；并在数据接收区显示接收到的字符。串口调试终端的设置：波特率115200，一个停止位，无校验位。-Realize this experiment, PS/2 interface with RS-232 data interface, PS/2 keyboard to press the button, through RS-232 automatic transmission to the host serial debug terminal (sscom32.exe) and data receiving display received characters. Serial debug terminal settings: 115200 baud rate, one stop bit, no parity bit.
Date : 2026-01-01 Size : 864kb User : skyy
[VHDL-FPGA-Verilog] PS2_RS232 DL : 0: 实现PS/2接口与RS-232接口的数据传输， PS/2键盘上按下按键，可以通过RS-232自动传送到主机的串口调试终端上（sscom32.exe）；并在数据接收区显示接收到的字符。串口调试终端的设置：波特率115200，一个停止位，无校验位-Realize PS/2 interface with RS-232 data interface, PS/2 keyboard to press the button, through RS-232 automatic transmission to the host serial debug terminal (sscom32.exe) and reception area in the data show receive characters. Serial debug terminal settings: 115200 baud rate, one stop bit, no parity bit
Date : 2026-01-01 Size : 1.34mb User : 张海风
[VHDL-FPGA-Verilog] uart_transmitter DL : 0: Very good info. for RS-232 transmitter VHDL code .
Date : 2026-01-01 Size : 1kb User : wan mi
[VHDL-FPGA-Verilog] uart_receiver DL : 0: Very good info. for RS-232 receive VHDL code .
Date : 2026-01-01 Size : 1kb User : wan mi
[VHDL-FPGA-Verilog] ECHO_DE2 DL : 0: Very good info. for RS-232 echo VHDL code .
Date : 2026-01-01 Size : 2kb User : wan mi
[VHDL-FPGA-Verilog] RS232 DL : 0: 基于VHDL的RS232通讯程序,包含完整的源代码,锁脚文件以及下载文件,可直接下载使用-VHDL based on the RS232 communication procedures, including complete source code, locking pin, as well as download files documents can be directly downloaded using
Date : 2026-01-01 Size : 16kb User : 陈泽涛
[VHDL-FPGA-Verilog] Button3_final DL : 0: 本程序用xilinx EDK9.1运行，通过microblaze软核，实现在sparton——3e板卡上的按键及开关的控制，通过RS－232与超级终端进行通信。-Xilinx EDK9.1 use this procedure to run through the MicroBlaze soft-core, realize in sparton- 3e board on the control buttons and switches, through the RS-232 communication with HyperTerminal.
Date : 2026-01-01 Size : 12.04mb User : wj
[VHDL-FPGA-Verilog] RS232 DL : 0: 本实验实现PS/2接口与RS-232接口的数据传输， PS/2键盘上按下按键，可以通过RS-232自动传送到主机的串口调试终端上（sscom32.exe）；并在数据接收区显示接收到的字符。串口调试终端的设置：波特率115200，一个停止位，无校验位。-Realize this experiment, PS/2 interface with RS-232 data interface, PS/2 keyboard to press the button, through RS-232 automatic transmission to the host serial debug terminal (sscom32.exe) and data receiving display received characters. Serial debug terminal settings: 115200 baud rate, one stop bit, no parity bit.
Date : 2026-01-01 Size : 713kb User : 李华
[VHDL-FPGA-Verilog] rs232_receiver DL : 0: VHDL implementation for an RS-232 receiver system.
Date : 2026-01-01 Size : 1kb User : mert
[VHDL-FPGA-Verilog] RS-232sender DL : 0: 一个串口RS-232 发送模块。基于VHDL语言。-A serial RS-232 send module. Based on the VHDL language.
Date : 2026-01-01 Size : 9kb User : 李超
[VHDL-FPGA-Verilog] uarts DL : 0: RS-232 interface example for FPGA/EDA developers
Date : 2026-01-01 Size : 2kb User : jools
[VHDL-FPGA-Verilog] 232 DL : 0: 实现PS/2接口与RS-232接口的数据传输，可以通过RS-232自动传送到主机的串口调试终端上并在数据接收区显示接收到的字符。-The realization of PS/2 port RS-232 interface with data transfer, RS-232 can be automatically sent to the host serial debug terminal and reception area in the data display received characters.
Date : 2026-01-01 Size : 15kb User : 包宰
[VHDL-FPGA-Verilog] rs-232vhdl DL : 0: it is the code for doing interfacing between computer and fpga board through rs-232.
Date : 2026-01-01 Size : 1kb User : sundaram
[VHDL-FPGA-Verilog] RS-232 DL : 0: verilog实现RS-232串口通信，经过功能仿真，完全能够行得通。-realise RS-232 by using verilog HDL
Date : 2026-01-01 Size : 356kb User : 曹蒙蒙
[VHDL-FPGA-Verilog] RS-232 DL : 0: RS-232发送接受模块，测试好用，满足一般要求-RS-232 transmit and receive modules, easy to use test, meet the general requirements
Date : 2026-01-01 Size : 2kb User : L

« 12 3 »