Search - random matlab

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[VHDL-FPGA-Verilog] itrl DL : 0: 交织本程序是自己编写的随机交织可以实现任意维度任意长度的交织比起其他的实现方法更具有推广型-Intertwined in this program is to prepare its own random interleaving can achieve any arbitrary length of the intertwined dimensions of the implementation is more than the other type has the extension
Date : 2025-12-18 Size : 4kb User : justin
[VHDL-FPGA-Verilog] interlace DL : 0: 根据MATLAB中的伪随机交织器产生的交织图案初始化到ROM中，从ROM中读取交织图案对输入数据进行交织。同时也可根据解交织图案进行解交织，同样的算法。-In accordance with MATLAB generated pseudo-random interleaver initialization pattern woven into the ROM, read from the ROM interwoven interwoven pattern of input data. Can also be deinterleaving deinterleaving pattern, the same algorithm.
Date : 2025-12-18 Size : 1kb User : 源天
[VHDL-FPGA-Verilog] BPSK DL : 0: 用于BPSK调制的自行设计，说明如下： 1.matlab.txt中的程序是matlab平台下的.mat格式。目的是输出一个64*4的矩阵，矩阵的每个元素都为0~255间的整数。矩阵每行的四个数是一个码元的四个抽样点的量化值。但由于当前码元通过升余弦滤波系统时，受到前后共6个码元的共同影响，所以是由6个码元共同决定。这6个码元是随机的，可能是0也可能是1（双极性时可能是-1也可能是+1），故6个码元共2^6=64种情况，所以产生的矩阵是64*4。最后逐行输出这256个数。 2.BPSK3中程序的目的是：将m序列通过滚降系数为0.3的升余弦滤波系统后的信号采样输出。 3.BPSK5中程序的目的是：将m序列通过滚降系数为0.5的升余弦滤波系统后的信号采样输出。 4.以上两个程序的运行平台为Quartus（verilog语言）。-BPSK modulation is used to design, as follows: 1.matlab.txt the program is under matlab platform. Mat format. Purpose is to output a 64* 4 matrix, each element is an integer between 0 and 255. Matrix of each line is a symbol of four the number of sampling points of the four quantitative value. However, due to the current symbol by raised cosine filtering system, before and after a total of six yards by the combined effect of element, it is shared by the six yards per decision. The 6 symbol is random, may be 0 may be 1 (may be bipolar may be+1-1), so a total of six yards per 2 ^ 6 = 64 kinds of situations, so the resulting matrix 64* 4. Finally, the number of progressive output of the 256. 2.BPSK3 purposes of the procedure is: m sequence of roll-off factor of 0.3 by the raised cosine filter system output after the signal sampling. 3.BPSK5 purposes of the procedure is: m sequence of roll-off factor of 0.5 by the raised cosine filter system output after the signal sampling.
Date : 2025-12-18 Size : 4kb User :
[VHDL-FPGA-Verilog] nsdge DL : 0: Rapid expansion of random spanning tree algorithm, Matlab wavelet analysis on complex, matlab implements five gray correlation degree computing model.
Date : 2025-12-18 Size : 9kb User : fennanning