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[VHDL-FPGA-Verilog] PWM_CT DL : 0: PWM调制输出、定时和计数控制器的芯片设计-PWM modulation output, timing and count controller chip design
Date : 2025-12-21 Size : 5kb User : 李利歌
[VHDL-FPGA-Verilog] 76_PID DL : 0: 一个非常好的电机转速控制器VHDL源代码设计-A very good motor speed controller VHDL design source code
Date : 2025-12-21 Size : 2kb User : linew
[VHDL-FPGA-Verilog] svpwm_full_nios DL : 0: 这是我毕业设计做的一个SVPWM同步永磁交流电机的控制系统，里面除了一个SVPWM的驱动算法之外，还有一个步进电机的控制器，以及基于QUARTUS7.2的NIOS II控制核心，通过PC的串口可以控制同步永磁交流电机和步进电机进行精确的定位。该系统较复杂，运用的知识也比较多，在SVPWM算法，PID算法，步进电机控制方面，NIOS II的串口编程等都有值得参考的地方。最好使用QUARTUS7.2编译，目标芯片是选用EP1C6Q240-This is my graduation project SVPWM make a permanent magnet AC synchronous motor control system, which apart from a driver SVPWM algorithm, there is a stepper motor controller, as well as QUARTUS7.2 based on the NIOS II control core, through PC serial port can be controlled permanent magnet AC synchronous motor and stepper motor for accurate positioning. The system is more complicated, the use of more knowledge, in the SVPWM algorithm, PID algorithm, stepper motor control, NIOS II serial programming, such as places are worth considering. QUARTUS7.2 compile the best use of the target chip is optional EP1C6Q240
Date : 2025-12-21 Size : 12.56mb User : 汉武帝
[VHDL-FPGA-Verilog] eda DL : 0: 利用FPGA可编程芯片及Verilog HDL语言实现了对直流电机PwM控制器的设计，对直流电机速度进行控制。介绍了用Verilog HDL语言编程实现直流电机PwM控制器的PwM产生模块、串口通信模块、转向调节模块等功能，该系统无须外接D／A转换器及模拟比较器，结构简单，控制精度高，有广泛的应用前景。同时，控制系统中引入上位机控制功能，可方便对电机进行远程控制。-Using FPGA programmable chip and Verilog HDL language for the design of DC motor PwM controller, DC motor speed control. Introduced with the Verilog HDL language programming controller PwM DC PwM generated module, serial communication module, steering adjustment module and other functions, the system is an external D/A converters and analog comparators, simple structure, high control precision, there a wide range of applications. Meanwhile, the introduction of PC control system control functions can be easily remote control the motor.
Date : 2025-12-21 Size : 4.07mb User : 杨汉轩
[VHDL-FPGA-Verilog] MyPWM DL : 0: 基于FPGA ALTERA EP2C5Q8208C8，自制PWM控制器，配合上位机定时器-based on FPGA ALTERA EP2C5Q，PWM controller,with MCU TIMER
Date : 2025-12-21 Size : 2.38mb User : 廖干洲
[VHDL-FPGA-Verilog] PWM-DCcontroller-design-on-FPGA DL : 0: 基于FPGA的直流电机PWM控制器设计，利用FPGA芯片设计了直流电机PWM控制器-DC motor PWM controller design based on FPGA
Date : 2025-12-21 Size : 213kb User :
[VHDL-FPGA-Verilog] 16f628a-PWM-controller DL : 0: PWM controller with LCD display. With the possibility of changing the frequency and pulse width.
Date : 2025-12-21 Size : 1kb User : Martin Serbezov
[VHDL-FPGA-Verilog] AAT1100-T1 DL : 0: 三通道可编程PWM控制器芯片，用于计算机主板散热风扇驱动-Three Channels PWM Controller
Date : 2025-12-21 Size : 1.03mb User : 方含柯
[VHDL-FPGA-Verilog] verilogHDL DL : 0: 针对C 语言编程者的Verilog 开发指南实例包括完全用软件实现的位脉冲PWM 控制器等-Fully implemented in software-bit pulse PWM controller instance for the C programming language Verilog Developer s Guide
Date : 2025-12-21 Size : 151kb User : 朴圣龙
[VHDL-FPGA-Verilog] RTL DL : 0: PWM controller in VHDL
Date : 2025-12-21 Size : 4kb User : spydeeps
[VHDL-FPGA-Verilog] PWM DL : 0: 基于FPGA的PWM控制器设计，包含ADC0820模块，按键扫描，PID，PWM控制器等模块，VHDL语言完成，已仿真通过-PWM controller design based on FPGA, including ADC0820 module, key scan, PID, PWM controllers and other modules, VHDL language completed, through simulation
Date : 2025-12-21 Size : 769kb User : hbxgwjl
[VHDL-FPGA-Verilog] pwm DL : 0: 使用VHDL实现可调的PWM控制器，便于初学者学习-Use VHDL to achieve an adjustable PWM controller, easy for beginners to learn
Date : 2025-12-21 Size : 1kb User : zsk
[VHDL-FPGA-Verilog] F0501 DL : 0: 汽车VCU控制器测试工装的程序，STM32单片机扩展总线读写FPGA内部RAM，DDS方式产生PWM，PWM频率，脉宽测量功能(Automotive VCU controller test tooling procedures, STM32 microcontroller expansion bus read and write FPGA, the internal RAM, DDS way to generate PWM, PWM frequency, pulse width measurement function)
Date : 2025-12-21 Size : 7.32mb User : nan211
[VHDL-FPGA-Verilog] PWM DL : 0: 利用Verilog语言设计一个PWM控制器，实现：控制器输入时钟1MHz；控制器输出脉冲周期1kHz，脉宽最小调节步长0.1%。(The Verilog language is used to design a PWM controller, which is realized: the controller input clock 1MHz; the controller output pulse cycle 1kHz, and the pulse width minimum adjustment step 0.1%.)
Date : 2025-12-21 Size : 61kb User : jcg17
[VHDL-FPGA-Verilog] pid_controller DL : 0: 项目总结了PID的基本算法和参数确定的方法，控制PWM步进电机(The PID controller IP core performs digital proportional-integral-derivative controller algorithm.)
Date : 2025-12-21 Size : 376kb User : 余平