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[VHDL-FPGA-Verilog] veriloghdl135 DL : 0: vhdl的学习资料，教程，一起进步，共勉-VHDL learning materials, curricula, progress together, share!
Date : 2025-12-19 Size : 171kb User : huang
[VHDL-FPGA-Verilog] VHDL_of_example DL : 0: 此为 VHDL 的示例程序,由于最近毕业设计要求使用这个编程,自己收集并整理了一些,供学习使用,希望和大家共同进步,有兴趣的也希望能和我一起讨论交流-this as examples of VHDL procedures, due to the recent graduation design requirements using the program, their collection by some for learning, hope and common progress. Interested also hoped to be able to discuss and exchange I
Date : 2025-12-19 Size : 51kb User : 钟毓秀
[VHDL-FPGA-Verilog] mux16_1 DL : 0: 本程序实现了对输入数路的16选1功能，需要的同志可以研究研究，共同进步-the realization of the import of a number of routes 16 election a function, the comrades need to be studies, and common progress
Date : 2025-12-19 Size : 86kb User : 龙小军
[VHDL-FPGA-Verilog] rfid_re DL : 0: VHDL实现 DDS。大家共享吧，一起学习，一起进步-VHDL realize DDS. U.S. to share it with learning, with progress
Date : 2025-12-19 Size : 846kb User : 赵颖
[VHDL-FPGA-Verilog] vhdl_example DL : 0: VHDL的例子，太好了，我是这样认为的，许多看过的同事都有同样的感受。让大家一起进步。-VHDL example of good, I think this is the case, and many colleagues have read have the same feelings. Progress so that all will work.
Date : 2025-12-19 Size : 165kb User : chendsh
[VHDL-FPGA-Verilog] EBCode21 DL : 0: 功能很强大！！！希望大叫多多指教，共同进步，一块发展-Function is very powerful! ! ! Hope that the exhibitions shouting and common progress, a development
Date : 2025-12-19 Size : 57kb User : liu
[VHDL-FPGA-Verilog] VHDL_src_files DL : 0: 这些是我在学习VHDL语言的过程中，自己试验过的以及自己编的一些程序，希望上传和大家分享一下，共同进步！谢谢！-These are my VHDL language in the learning process, and tested their own some of the procedures, I hope to upload and share with you, and common progress! Thanks!
Date : 2025-12-19 Size : 70kb User : lijq
[VHDL-FPGA-Verilog] 61EDA_D721 DL : 0: 8*8乘法器设计，和大家共享，互相学习，共同进步-8* 8 multiplier design, and for all to share and learn from each other and progress together
Date : 2025-12-19 Size : 29kb User : zhao yang
[VHDL-FPGA-Verilog] verilog_lecture DL : 0: 本文是卡内基梅隆大学的verilog讲义，写作的角度与中文教材的角度有所不同，看了后会有一定的收获和进步。-Carnegie Mellon University This article is the verilog lectures, writing perspective and the perspective of Chinese teaching materials are different, there will be certain after reading the harvest and progress.
Date : 2025-12-19 Size : 229kb User : 潘
[VHDL-FPGA-Verilog] mux4 DL : 0: 这是个四输入乘法器，还可以进步扩充端口-This is a four-input multiplier, but also the progress of the expansion of port
Date : 2025-12-19 Size : 341kb User : lee
[VHDL-FPGA-Verilog] Vhdl1 DL : 0: Top Level VHDL Code -- simulate the relatively slow progress of an elevator car by dividing the -- clock down by an outrageously high number and scanning the car registers for -- an elevator s next -- (normally the signals used below would be IO pins on the chip, but we have -- no physical elevator, so this is a kind of "diagnostic mode")-Top Level VHDL Code -- simulate the relatively slow progress of an elevator car by dividing the -- clock down by an outrageously high number and scanning the car registers for -- an elevator s next -- (normally the signals used below would be IO pins on the chip, but we have -- no physical elevator, so this is a kind of "diagnostic mode")
Date : 2025-12-19 Size : 3kb User : Victor
[VHDL-FPGA-Verilog] zhengtaoEDAtest DL : 0: FPGA入门级学习，自己试验过的VHDL程序，实践学习后进步很快。-Entry-level FPGA learning that he tested the VHDL program, after learning the practice of making rapid progress.
Date : 2025-12-19 Size : 2.27mb User : sunzhihui
[VHDL-FPGA-Verilog] synplify_for_xilinx DL : 0: 英文资料，综合工具synplify 对xilinx的支持。英文不错的进-Information in English, integrated tools synplify on xilinx support. Good progress in English
Date : 2025-12-19 Size : 223kb User : 李明
[VHDL-FPGA-Verilog] RunningLED(1) DL : 0: 很有用的希望帮到大家学习vhdl语言我们大家一起去的进步-Useful to help them to learn vhdl want us to go with the language of progress
Date : 2025-12-19 Size : 5.38mb User : 钟鸣
[VHDL-FPGA-Verilog] res DL : 1: 基于FPGA的六路抢答器的设计，是我毕业设计中的一部分内容，花了很长时间编写的，通过的仿真和实验调试，希望大家喜欢，一起交流，一起进步-FPGA-based design of six-way Responder is my part in the graduation, took a long time writing, through the simulation and experimental testing, hope you like it, with the exchange, together with progress
Date : 2025-12-19 Size : 1.24mb User : 飞天德
[VHDL-FPGA-Verilog] VHDL-Responder-Course-Design DL : 0: 开始键按下后，8个进度指示灯依次点亮，之后开始抢答。4个按键开关代表4个抢答键，由数码管显示最先按下的开关序号，表示此号码抢答成功。若在进度灯全亮之前有任意键被按下，则表示有人犯规！系统结构描述：此系统共包括4个板块，分别是输入板块、计数器板块、数码显示器板块、判断板块，各功能组合一起构成一个完整的抢答器。-Start key is pressed, 8 progress lights were lit, and then answer in the beginning. 4 key switches on behalf of four answer in key pressed by the digital display the switch serial number first, that this number Responder success. If the light all light in the progress before the any key is pressed, it means that some foul! System Architecture Description: This system includes a total of 4 sections, namely the input plate, counter plate, digital display board, determine the plate, the combination of features together constitute a complete Responder.
Date : 2025-12-19 Size : 365kb User : 竹下寺宁
[VHDL-FPGA-Verilog] Verilog DL : 0: verilog数字系统学习教程，设和不同人群，通俗易懂，共同学习进步-verilog digital system tutorials, design, and different groups of people, easy to understand, common learning progress
Date : 2025-12-19 Size : 6.81mb User : 宫文展
[VHDL-FPGA-Verilog] Verilog-HDL DL : 0: 本文档提供了非常完整的Verilog HDL语言代码源程序，希望大家多多借鉴，我们一起进步，谢谢！-This document provides very complete Verilog HDL language code source program, hope everybody many reference, we together with progress, thank you!!!!!
Date : 2025-12-19 Size : 31kb User : 王萌
[VHDL-FPGA-Verilog] spi-uart DL : 0: 这个程序是C8051F30x设备通过 spi 通讯然后从串口发送的例程具有 spi 跟串口的初始化操作-This program sets up the GPIO pins on the C8051F30x device for the correct functionality, then uses the SPI_Transfer function to send and receiveinformation through the SPI pins. As information is sent, the progress othe program is sent out through the UART to be monitored on a connected terminal program
Date : 2025-12-19 Size : 11kb User :
[VHDL-FPGA-Verilog] VHDL DL : 0: 本设计中选用目前应用较广泛的VHDL硬件电路描述语言，实现对路口交通灯系统的控制器的硬件电路描述，在Altera公司的EDA软件平台MAX+PLUSⅡ环境下通过了编译、仿真，并下载到CPLD器件上进行编程制作，实现了交通灯系统的控制过程。-And select and use Description Language applying broader VHDL hardware circuit at present in capital being designed, the hardware circuit coming true to systematic controller of crossing traffic light describes that, have passed compiling , have simulated under EDA of Altera company software platform MAX+ PLUS II environment, download the control procedure having made , realizing traffic light systematically to the programming being in progress on CPLD component.
Date : 2025-12-19 Size : 260kb User : 陈金峰

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