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[VHDL-FPGA-Verilog] ACEXep1k10tc100 DL : 0: 喷绘机编程!-Printer programming!
Date : 2025-12-27 Size : 170kb User : zhenghongkai
[VHDL-FPGA-Verilog] ppoc DL : 0: 简单的POC实现与打印机，CPU的连接可以中断或查询方式。-POC realize a simple printer, CPU connections can be interrupted or query.
Date : 2025-12-27 Size : 166kb User : 刘超
[VHDL-FPGA-Verilog] M-150_tm_eng DL : 1: M-150II打印机芯开发资料,广泛用于出租车记价器与消防记录仪!-M-150II Printer core development of information, widely used in taxi price in mind logger browser with fire!
Date : 2025-12-27 Size : 1.57mb User : yinhuihuang
[VHDL-FPGA-Verilog] POC DL : 0: 东南大学学生数字系统设计实验：用VHDL语言编写Printer与CPU互连的接口程序-Southeast University students in the experimental digital system design: VHDL language with Printer and CPU interface interconnection procedures
Date : 2025-12-27 Size : 1kb User : 田华梅
[VHDL-FPGA-Verilog] CPU DL : 0: 实现简单CPU功能的源码，可以实现加减乘除和移位功能，VHDL代码，程序运行在MAX PULS和Quartua上。-The purpose of this project is to design and simulate a parallel output controller (POC) which acts an interface between system bus and printer. The Altera’s Maxplus Ⅱ EDA tool is recommended and provided for simulation.
Date : 2025-12-27 Size : 4.28mb User : 灿烂六月
[VHDL-FPGA-Verilog] poc DL : 0: 连接CPU与外部器件printer的接口元件，用VHDL语言编写，可进行仿真-CPU and external devices connected printer interface components, with the VHDL language, can be simulated
Date : 2025-12-27 Size : 527kb User : Sophie
[VHDL-FPGA-Verilog] POC-Project DL : 0: 系统总线与打印机之间的借口：并行输出控制器POC的设计。涉及POC与CPU，POC与printer之间的握手操作。-Between the system bus and an excuse for the printer: parallel output controller POC design. Involved in POC and CPU, POC and the printer handshake between the operations.
Date : 2025-12-27 Size : 626kb User : ilmf
[VHDL-FPGA-Verilog] poc DL : 0: 可以并行的控制多个端口的POC控制器，包括打印机端口等多个端口，且波形模拟通过-Can control multiple ports in parallel POC controllers, including the printer port and other ports, and analog waveform through
Date : 2025-12-27 Size : 1kb User : shenhaoxing
[VHDL-FPGA-Verilog] POC DL : 0: 基于VHDL开发POC接口代码，主要用于cpu和打印机之间的数据处理控制-VHDL code development based POC interfaces, cpu and the printer is mainly used for data processing control
Date : 2025-12-27 Size : 5kb User : 陈魁东
[VHDL-FPGA-Verilog] Printer DL : 0: The internal circuit of the simulated printer module, in a students course design - A parallel output controller (POC) .-The internal circuit of the simulated printer module, in a students course design - A parallel output controller (POC) .
Date : 2025-12-27 Size : 2kb User : szfzafa
[VHDL-FPGA-Verilog] SS205PFPGA DL : 0: 利用FPGA实现对SS205的热敏打印机的控制，解决了在LINUX系统等实时性不高的系统中要求高实时性的热敏打印机控制问题。-Using FPGA to realize the control of SS205 in the thermal printer to solve the real-time systems in LINUX system is not high demanding real-time control of thermal printer.
Date : 2025-12-27 Size : 281kb User : 何祥
[VHDL-FPGA-Verilog] POC_all DL : 0: poc即为cpu与外部设备，比如打印机的接口，用VHDL的编程来实现poc功能的仿真-poc is the cpu with an external device, such as the printer' s interface, programming with VHDL simulation capabilities to achieve poc
Date : 2025-12-27 Size : 899kb User : 苏佳佳
[VHDL-FPGA-Verilog] parallel-output-controller-(POC) DL : 0: 并行输出控制器，实现CPU与打印机之间的通信，程序基于VHDL语言，内附完整实验报告与仿真图像-The purpose of this project is to design and simulate a parallel output controller (POC)which acts an interface between system bus and printer. The Altera’s Quartus II EDA tool is recommended and provided for simulation.
Date : 2025-12-27 Size : 73kb User : 陈鹏
[VHDL-FPGA-Verilog] poc DL : 0: The purpose of this project is to design and simulate a parallel output controller (POC) which acts an interface between system bus and printer. The Altera’s Maxplus II EDA tool is recommended and provided for simulation.
Date : 2025-12-27 Size : 417kb User : 程梦飞
[VHDL-FPGA-Verilog] printer DL : 1: VHDL模拟示波器文字显示 32x32字符显示 DA使用AD9767-VHDL analog oscilloscope display 32x32 characters text display using AD9767 DA
Date : 2025-12-27 Size : 1.51mb User : 朱棣
[VHDL-FPGA-Verilog] motorpasso DL : 0: Stepper motor pulse generator. This core receives data through system interconnect fabric (bus slave),generates movements pulse and direction signals and provide a fire signal for printer machines. Need to configure prescaler.
Date : 2025-12-27 Size : 2kb User : Will
[VHDL-FPGA-Verilog] POC DL : 0: 用VHDL语言设计一个并行输出控制器POC，作为系统总线个打印机的借口-The purpose of this project is to design and simulate a parallel output controller(poc) which acts an interface between system bus and printer. The Altera’s Maxplus II EDA tool is recommended and provided for simulation.
Date : 2025-12-27 Size : 465kb User : 张帆帆
[VHDL-FPGA-Verilog] poc04008307 DL : 0: 设计一个并行输出控制器，可以连接系统总线和打印机- The purpose of this project is to design and simulate a parallel output controller (POC) which acts an interface between system bus and the printer.
Date : 2025-12-27 Size : 441kb User : anny
[VHDL-FPGA-Verilog] driving-lcd-a-port-interface DL : 0: Driving a character type LCD from a PC printer port.
Date : 2025-12-27 Size : 104kb User : Asilas Molis
[VHDL-FPGA-Verilog] CH352DS1 DL : 0: CH352 English DataSheet PCI dual UART,used for PCI to dual UART,PCI to printer port(parallel port),this datasheet is about PCI dual UART
Date : 2025-12-27 Size : 194kb User : atmega8pl

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