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[VHDL-FPGA-Verilog] i2c DL : 1: I2C端口的FPGA实现，网上较多，但发现不少有问题，这个是在网上代码的基础上修改过，验证可行。-I2C port FPGA, online more, but found that many problems This is a code on the Internet on the basis of the revised test feasible.
Date : 2025-12-26 Size : 1kb User : 贾明
[VHDL-FPGA-Verilog] SDRAM DL : 0: 模块采用网上的模块，自己进行测试，在测试过程中了解其使用方法。经过测试，存进去的数据正确读取出来。-The module uses online modules, test yourself, to understand its use in the testing process. Been tested and stored inside the data read correctly.
Date : 2025-12-26 Size : 3.91mb User : daxws
[VHDL-FPGA-Verilog] mj10 DL : 0: 实现门禁系统，可以做网店实战的项目，对接数据库，不过里面没有数据库想对应的测试数据(The implementation of the entrance guard system, can do online shop actual projects, docking database, but there is no database to corresponding test data in it.)
Date : 2025-12-26 Size : 20.46mb User : qqb