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[VHDL-FPGA-Verilog] random data gen（vhdl） DL : 0: 任意数据发生器的源代码-arbitrary data source code generator
Date : 2025-12-29 Size : 95kb User : 王锋
[VHDL-FPGA-Verilog] fsm8051 DL : 1: ：首先介绍了DS--UWB系统的的发射与接收模型，然后分析了利用滑动相关法对信道进行估讣，并巾此给出了不同RAKE接收机RAKE合成权系数选取方案。对接收机采用最大比(MRC)、最小均方误差(MM SE)及带均衡器的(MRC)合并系数选取的误码性能进行了仿真和对比。结果表明了带均衡器的MRC—RAKE只用较少的分支就可以达到接收性能明显优于MMSE—RAKE的程度。尤其在信噪比比较大时。这种优势更加明显。-: First of all, the introduction of the DS UWB system model of the launch and reception, and then analyzed using the sliding correlation method for estimation of channel obituary, and towels, this gives the RAKE receiver RAKE synthesis of different weights to select the program. On the receiver using maximal ratio (MRC), minimum mean square error (MM SE) and band equalizer (MRC) combined coefficient selected BER simulation and comparison. The results show that the equalizer with MRC-RAKE only with fewer branches on the receiver performance can be achieved significantly better than MMSE-RAKE level. Particularly in the relatively large signal to noise ratio. This advantage becomes even more evident.
Date : 2025-12-29 Size : 1kb User : 季昀
[VHDL-FPGA-Verilog] oc8051_defines DL : 0: ：首先介绍了DS--UWB系统的的发射与接收模型，然后分析了利用滑动相关法对信道进行估讣，并巾此给出了不同RAKE接收机RAKE合成权系数选取方案。对接收机采用最大比(MRC)、最小均方误差(MM SE)及带均衡器的(MRC)合并系数选取的误码性能进行了仿真和对比。结果表明了带均衡器的MRC—RAKE只用较少的分支就可以达到接收性能明显优于MMSE—RAKE的程度。尤其在信噪比比较大时。这种优势更加明显。-: First of all, the introduction of the DS UWB system model of the launch and reception, and then analyzed using the sliding correlation method for estimation of channel obituary, and towels, this gives the RAKE receiver RAKE synthesis of different weights to select the program. On the receiver using maximal ratio (MRC), minimum mean square error (MM SE) and band equalizer (MRC) combined coefficient selected BER simulation and comparison. The results show that the equalizer with MRC-RAKE only with fewer branches on the receiver performance can be achieved significantly better than MMSE-RAKE level. Particularly in the relatively large signal to noise ratio. This advantage becomes even more evident.
Date : 2025-12-29 Size : 4kb User : 季昀
[VHDL-FPGA-Verilog] pc DL : 0: ：首先介绍了DS--UWB系统的的发射与接收模型，然后分析了利用滑动相关法对信道进行估讣，并巾此给出了不同RAKE接收机RAKE合成权系数选取方案。对接收机采用最大比(MRC)、最小均方误差(MM SE)及带均衡器的(MRC)合并系数选取的误码性能进行了仿真和对比。结果表明了带均衡器的MRC—RAKE只用较少的分支就可以达到接收性能明显优于MMSE—RAKE的程度。尤其在信噪比比较大时。这种优势更加明显。-: First of all, the introduction of the DS UWB system model of the launch and reception, and then analyzed using the sliding correlation method for estimation of channel obituary, and towels, this gives the RAKE receiver RAKE synthesis of different weights to select the program. On the receiver using maximal ratio (MRC), minimum mean square error (MM SE) and band equalizer (MRC) combined coefficient selected BER simulation and comparison. The results show that the equalizer with MRC-RAKE only with fewer branches on the receiver performance can be achieved significantly better than MMSE-RAKE level. Particularly in the relatively large signal to noise ratio. This advantage becomes even more evident.
Date : 2025-12-29 Size : 1kb User : 季昀
[VHDL-FPGA-Verilog] 1111 DL : 0: 基于Verilog-HDL的转子振动噪声电压峰值检测，值得学习啊，-Verilog-HDL based on the rotor vibration noise voltage peak detector, it is worth learning ah,
Date : 2025-12-29 Size : 2.19mb User : 王朱忠
[VHDL-FPGA-Verilog] vhdl DL : 0: 伪随机码发生器的VHDL实现随着通信理论的发展，早在20世纪40年代，香农就曾指出，在某些情况下，为了实现最有效的通信，应采用具有白噪声的统计特性的信号。另外，为了实现高可靠的保密通信，也希望利用随机噪声。然而，利用随机噪声最大困难是它难以重复产生和处理。直到60年代，伪随机噪声的出现才使这一难题得到解决-Pseudo-random code generator for VHDL realize communication with the development of the theory, as early as the 20th century, 40 years, Shannon has pointed out that in some cases, in order to realize the most effective communications, should be used with the statistical properties of white noise signal . In addition, in order to realize highly reliable secure communication, but also wish to take advantage of random noise. However, the use of random noise the greatest difficulty is that it difficult to repeat the generation and treatment. Until 60 years, the emergence of pseudo-random noise so that this problem only be solved
Date : 2025-12-29 Size : 212kb User : 张之晗
[VHDL-FPGA-Verilog] CORRECE DL : 0: 使用MATLAB完成CDMA系统的相关接收机，其中哈达码矩阵为128阶，仿真比特信噪比为-10DB-CDMA system using MATLAB to complete the relevant receivers, which Hadamard matrix of 128 bands, simulation-10DB-bit signal to noise ratio for
Date : 2025-12-29 Size : 1kb User : 王莉
[VHDL-FPGA-Verilog] PhaseNoise DL : 0: 小数分频技术解决了锁相环频率合成器中的频率分辨率和转换时间的矛盾, 但是却引入了严重的相位噪声, 传统的相位补偿方法由于对Aö D 等数字器件的要求很高并具有滞后性实现难度较大。$2 调制器对噪声具有整形的功能, 因而将多阶的$2 调制器用于小数分频合成器中可以很好地解决他的相位噪声的问题, 大大促进了小数分频技术的发展和应用。文章最后给出了在GHz 量级上实现的这种新型小数分频合成器的应用电路, 并测得良好的相噪性能。-Fractional-N technology to solve the PLL frequency synthesizer in the frequency resolution and conversion time of contradictions, but the introduction of a serious phase noise, the traditional method of phase compensation A? D because of the number of devices, such as demanding and have the lag is more difficult to achieve. $ 2 modulator with noise shaping function, and thus will be more than the $ 2-order modulator for fractional-N synthesizer can be a good solution to his problem of phase noise, contributed significantly to the fractional-N technology development and applications. Finally, the article in the GHz order to achieve this new fractional-N synthesizer of the application circuit, and measured a good phase noise performance.
Date : 2025-12-29 Size : 280kb User : 朱成发
[VHDL-FPGA-Verilog] Verilog_code_for_AWGN DL : 0: verilog实现awgn信道噪声的代码，支持可变的信噪比。利用移位寄存器来实现伪随机序列。-verilog code for implementation of awgn channel noise. support variable snr. use LSFR to implement the pseudo random sequence.
Date : 2025-12-29 Size : 10.07mb User : xiejin
[VHDL-FPGA-Verilog] noise DL : 0: 基于FPGA的噪声产生电路，用MATLAB设计噪声仿真程序，产生仿真数据的方法。并利用FPGA模拟信号。其中有详尽的matlab仿真程序，FPGA仿真结果以及总的设计报告。-Noise generating circuit based on FPGA, using MATLAB simulation program designed noise, resulting simulation data. Analog signal using the FPGA. Which detailed matlab simulation program, FPGA simulation results and the overall design of the report.
Date : 2025-12-29 Size : 1.22mb User : hp
[VHDL-FPGA-Verilog] mid_filter DL : 0: 中值滤波的实现，用于图像的预处理。取出图像噪声-Implementation of median filter for image preprocessing. Remove image noise
Date : 2025-12-29 Size : 5kb User : 一
[VHDL-FPGA-Verilog] noise DL : 0: 随机噪声产生代码。所输出的随机噪声可以用于模拟信道中的加性噪声。-Random noise generated code. The output of the random noise can be used to simulate the channel additive noise.
Date : 2025-12-29 Size : 1kb User : simulin_2008
[VHDL-FPGA-Verilog] Digital-Noise-Defect DL : 0: 一本很好的关于介绍检测数字噪声的起源的书籍-this is a good book for Digital Noise Monitoring of Defect Original
Date : 2025-12-29 Size : 2.03mb User : 袁园
[VHDL-FPGA-Verilog] Noise-on-the-PLL-loop-bandwidth DL : 0: 一篇介绍的比较详细的关于锁相环噪声与环路带宽的文档-Noise on the PLL loop bandwidth of the document
Date : 2025-12-29 Size : 220kb User : 肖飞
[VHDL-FPGA-Verilog] Low-phase-noise DL : 0: 能够完成低相噪、低杂波数字锁相环路滤波器-Low phase noise, low clutter digital phase-locked loop filter design
Date : 2025-12-29 Size : 756kb User : 郑晔桦
[VHDL-FPGA-Verilog] medianfilter DL : 1: 图像滤波中的中值滤波，有效滤除椒盐噪声，使用verilog语言编写-Image filtering in the median filter, effectively filter out salt and pepper noise, using verilog language
Date : 2025-12-29 Size : 3.11mb User : 钱军
[VHDL-FPGA-Verilog] noise.vhd DL : 0: noise in vhdl format
Date : 2025-12-29 Size : 9kb User : suhirdham
[VHDL-FPGA-Verilog] noise-cancellation-.vhd DL : 0: noise cancellation in vhdl format
Date : 2025-12-29 Size : 9kb User : suhirdham
[VHDL-FPGA-Verilog] noise-cancellation DL : 0: 脉冲噪声消除对输入数据循环累加并求平局比较-noise cancellation source code
Date : 2025-12-29 Size : 16.4mb User : ssaaa
[VHDL-FPGA-Verilog] noise DL : 0: 使用FPGA搭建NOISE||内核，在内核基础上进行工程建立。(Using the FPGA to build NOISE || kernel, based on the kernel to build the project.)
Date : 2025-12-29 Size : 18.8mb User : 湘城旧事

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