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[VHDL-FPGA-Verilog] 65filter DL : 0: 65位FIR数字滤波器的设计~~其中有通过仿真得出得数据 ~可以通过数据输入完成滤波实验~对数字滤波器得整个算法进行了分析包括输入分组相加然后相乘得过程-65 FIR digital filter design ~ ~ with simulation data to come in through the importation of data from experiments completed filtering of the digital filter in the whole algorithm analysis including input a sum then multiply in the process
Date : 2025-12-28 Size : 3kb User : 凌燕
[VHDL-FPGA-Verilog] multiply DL : 1: 好用的浮点乘法器，可完成32位IEEE格式的浮点乘法，经过仿真通过-Easy to use floating-point multiplier, to be completed by 32-bit IEEE format floating-point multiplication, through simulation through
Date : 2025-12-28 Size : 1kb User : gulu
[VHDL-FPGA-Verilog] multiply DL : 0: 乘法器的vhdl语言描述.本人调试已经通过-Multiplier described in VHDL language. I have been through the debugging
Date : 2025-12-28 Size : 29kb User : hjj
[VHDL-FPGA-Verilog] multiply DL : 0: Verilog hdl语言常用乘法器设计，可使用modelsim进行仿真-Verilog hdl language commonly used multiplier design, can use the ModelSim simulation
Date : 2025-12-28 Size : 2kb User : 许立宾
[VHDL-FPGA-Verilog] multiply DL : 0: 由verilog编写的乘法器，通过两个文件的调用实现。由于子模块的调用使得程序简化了许多。-Prepared by the Verilog multiplier, through the realization of the two documents call. As the sub-modules to simplify the procedure call makes a lot.
Date : 2025-12-28 Size : 3kb User : 金夕
[VHDL-FPGA-Verilog] fir_parall DL : 0: 基于verilog的fir滤波器设计，用的并行结构。在前面基础上加入四级流水（加法器，并行乘法器，乘法结果相加两级），通过验证。-Verilog-based design of fir filter using the parallel architecture. In front of the basis of adding four water (adder, parallel multiplier, multiply the result of the sum of two), through the verification.
Date : 2025-12-28 Size : 3kb User : 张堃
[VHDL-FPGA-Verilog] cpu DL : 0: 用VHDL语言设计简单的CPU，重点设计微操作代码，然后设计CPU各组成模块，最后根据设计的微操作设计微指令，验证设计的正确性。可基本实现加、减、乘、除、移位、循环等操作。-VHDL language is designed to be simple to use the CPU, the focus of the design of micro-operation code, and then design the components of CPU module designed the final design of the micro-operation microinstruction to verify the correctness of the design. Can achieve the basic add, subtract, multiply, divide, transfer, recycling and other operations.
Date : 2025-12-28 Size : 1.21mb User : Rachel
[VHDL-FPGA-Verilog] float_data_multiple_use_fixed_pipeline_verilog_pro DL : 0: 采用fpga做小数运算的程序，使用了三级流水线技术，这是学习流水线和定点小数乘法很好的例子！-a program of float multiply, using 3-stage pipeline technology
Date : 2025-12-28 Size : 1kb User : xietianjiao
[VHDL-FPGA-Verilog] multilyUnit1 DL : 0: a verilog programmed multiply unit algorithm
Date : 2025-12-28 Size : 149kb User : ash
[VHDL-FPGA-Verilog] multiplyUnit2 DL : 0: verilog multiply algorithm
Date : 2025-12-28 Size : 2kb User : ash
[VHDL-FPGA-Verilog] LEDjun DL : 0: 此程序能够实现4位二进制乘法，可以放心使用，可能不太全，第一次上传，不大明白-4*4 multiply which can be used that s all.
Date : 2025-12-28 Size : 360kb User : 赵伟
[VHDL-FPGA-Verilog] code DL : 0: This project is "digital serial multiplier". this proh=ject is used to multiply the serial data with parallel data. the source code is writtenby using vhdl.
Date : 2025-12-28 Size : 5kb User : RUPA KRISHNA
[VHDL-FPGA-Verilog] float_mul_verilog DL : 1: 浮点乘法verilog代码，浮点格式遵循 IEEE754 标准。-Float Point Multiply , im verilog
Date : 2025-12-28 Size : 2kb User : gongwen
[VHDL-FPGA-Verilog] presentar DL : 0: Verilog code calculator, add, rest, multiply, and increment-Verilog code calculator, add, rest, multiply, and increment
Date : 2025-12-28 Size : 1kb User : jaja12
[VHDL-FPGA-Verilog] multiplier-accumulator(vhdl) DL : 0: 用VHDL语言描述和实现乘法累加器设计,4位的被乘数X和4位的乘数Y输入后，暂存在寄存器4位的寄存器A和B中，寄存器A和B的输出首先相乘，得到8位乘积，该乘积再与8位寄存器C的输出相加，相加结果保存在寄存器C中。寄存器C的输出也是系统输出Z。(原创，里面有乘法部分和累加部分可以单独提出来，很好用) -With the VHDL language to describe the design and realization of multiplier-accumulator, four of multiplicand X and 4-bit multiplier Y input, the temporary 4-bit registers in the register A and B, registers A and B multiplied by the output of the first, to be 8-bit product, the product further with the 8-bit output of register C, the sum of, the sum of the results stored in register C,. The output register C is also the system output Z. (Original, which are multiply and accumulate some part may be raised separately, very good use)
Date : 2025-12-28 Size : 945kb User : jlz
[VHDL-FPGA-Verilog] multiply DL : 0: 简单的乘法器，用Verilog实现 multiply-multiply
Date : 2025-12-28 Size : 1kb User :
[VHDL-FPGA-Verilog] CourseDesign DL : 0: 用Verilog实现一位原码浮点数乘法器，按照累加的方式，逐位相乘，再相加。-Verilog realization of an original code with floating point multiplier, in accordance with the cumulative way, bit by bit multiply, then add.
Date : 2025-12-28 Size : 240kb User : 李伟彬
[VHDL-FPGA-Verilog] add8 DL : 0: 用VHDL语言实现的八位计数器可进行简单的加减乘除运算-It is a counting device with eight-bit that could plus ,subtract ,multiply and divide.
Date : 2025-12-28 Size : 3kb User : 邓
[VHDL-FPGA-Verilog] multiply DL : 0: vhdl语言编写，实现了任意位数的两个数的乘法器-Realize any two-digit number of multiplier
Date : 2025-12-28 Size : 1mb User : 王鹏
[VHDL-FPGA-Verilog] Multiply DL : 0: 四进位乘法器，在modelSim有仿真结果。-4bits Multiply,having stimulation in modelSim.
Date : 2025-12-28 Size : 153kb User : 姜华

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