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[VHDL-FPGA-Verilog] 基于FPGA的李沙育图形发生器 DL : 0: 这是一个用MAX+PLUSII开发FPGA（1K30器件）开发的李沙育图形发生器（硬件描述语言部分）。-This is a development with MAX PLUSII FPGA (1K30 device) developed Lissajous Pattern Generator (hardware description language).
Date : 2025-12-23 Size : 773kb User : 孔玉
[VHDL-FPGA-Verilog] maxshiyan DL : 0: 大学vhdl语言实验大全,基于max-plus2平台,内有8-3译码器,8位加法器,数字钟，数码显示，74ls138，8，4位计数器，d，rs触发器，加法器，交通灯等，此原码基于长江大学可编程器件实验箱,如要运行在其他平台上需要重新定义管脚-University VHDL language experiment Daquan, based on the max-plus2 platform within 8-3 decoder, 8 Adder, digital clock, digital display, 74ls138, 8,4-bit counter, d, rs triggers, Adder, traffic lights, the original code based on the Yangtze University programmable devices experimental box, To run on other platforms need to be redefined pin
Date : 2025-12-23 Size : 845kb User : 田晶昌
[VHDL-FPGA-Verilog] Booth_Multiplier DL : 0: 布斯乘法器的VHDL程序,下載後直接解壓縮複製貼上到你的EDATOOL就可以.-Booth multiplier VHDL procedures downloaded directly extract copy affixed to the EDATOOL you can.
Date : 2025-12-23 Size : 1kb User : 韓堇
[VHDL-FPGA-Verilog] vhdl-2 DL : 0: Date : 2025-12-23 Size : 58kb User : lileiming
[VHDL-FPGA-Verilog] VHDL-Clock DL : 0: 用VHDL语言写的时钟程序。采用模块化编程。可在EPM7128芯片上下载。编译环境可用Maxplus或Quartus。-write VHDL clock procedures. Modular programming. The EPM7128 chips download. Build environment or Quartus Maxplus available.
Date : 2025-12-23 Size : 4kb User : 单单
[VHDL-FPGA-Verilog] clock_CPLD DL : 0: 采用MaxPlusII写的一个小时钟程序，也是供初学参考。呵呵。注///版主，开发环境里面没有MaxPlusII.-MaxPlusII used to write a small clock procedures, as well as reference for beginners. Ha ha. Note///moderator, development environment there's no MaxPlusII.
Date : 2025-12-23 Size : 793kb User : Backy
[VHDL-FPGA-Verilog] shuzizhong05 DL : 0: MAX+plus II 9.23 Baseline-MAX plus Baseline II 9.23
Date : 2025-12-23 Size : 252kb User : 冬海
[VHDL-FPGA-Verilog] DigitalClockVHDL DL : 0: 多功能电子时钟的VHDL源代码。使用MAX+PLUS II进行编译。该文档有详细的说明和程序注释。-VHDL source code. Use MAX PLUS II computer. The document is described in detail in the Notes and procedures.
Date : 2025-12-23 Size : 82kb User : wangyiran
[VHDL-FPGA-Verilog] chengxufengxiang DL : 0: 这些程序我用MAX+PlusII软件测试均能通过编译，程序本身不复杂，旨在为刚接触VHDL语言的朋友提供一些样例，以便了解VHDL语言的基本构成。如果要运行测试，则新建文件名应于程序中实体名一致，文件后缀“.vhd”，不推荐直接通过复制、粘贴的方法录入程序，可能会引入错误字符。 -these procedures I used MAX PlusII Software Testing pass compiler, the process itself is not complicated. for the fourth year to VHDL friend to provide some examples in order to understand the VHDL basic components. If testing, the new file name in the process should be entity line extensions. " Vhd " not recommended directly by copying and pasting the time of admission procedures, the potential introduction of the wrong characters.
Date : 2025-12-23 Size : 1kb User : zhaoting
[VHDL-FPGA-Verilog] myproject DL : 0: 四位全加器，VHDL语言，max+plusII平台做的-Four full-adder, VHDL language, max+ PlusII platform to do
Date : 2025-12-23 Size : 55kb User : 邱飞
[VHDL-FPGA-Verilog] taxi-vhdl DL : 0: 出租车计费器硬件描述语言出租车计费器 MAX+PLUS软件数字系统-Taxi billing hardware description language taxi meter MAX+ PLUS software digital systems
Date : 2025-12-23 Size : 47kb User : aneeee
[VHDL-FPGA-Verilog] electoniclock DL : 0: 摘　要: 数字密码锁主要完成上锁、密码输入、密码核对、开启电锁、密码修改等功能.数字密码锁的设计电路主要包括 11 个模块 ,各模块由相应的 VHDL 程序具体实现并分别进行了 MAX + PLUS II 时序仿真. 最后 ,在 MAX + PLUS Ⅱ环境下进行了整体电路的模拟仿真 ,结果表明 ,整个设计满足要求.
Date : 2025-12-23 Size : 696kb User : 孙光华
[VHDL-FPGA-Verilog] 0097 DL : 0: MAX+plus II编译的模30加法计数器，简单的与非门组成！-MAX+ Plus II compiler module adder 30 counters, a simple composition with the non-door!
Date : 2025-12-23 Size : 13kb User : LEE
[VHDL-FPGA-Verilog] MAX-PLUSII-soft DL : 0: MAX+PLUSII软件是一个功能强大，容易使用的软件包，它可以以图形方式、文字输入方式（AHDL、VHDL和VERILOG）和波形方式输入设计文件，可以编译并形成各种能够下装到EPROM和各种ALTERA器件的文件，还可以进行仿真以检验设计的准确性，下面举例说明该软件的使用-MAX+ PLUSII software is a powerful, easy-to-use software package, which can graphically, text input methods (AHDL, VHDL and VERILOG) and waveform enter design documents can be compiled and form can be downloaded to a variety of EPROM and ALTERA documents a variety of devices can also be used for simulation to test the accuracy of the design, the following examples to illustrate the use of the software
Date : 2025-12-23 Size : 122kb User : 徐靖
[VHDL-FPGA-Verilog] a_block_with_several_functions_with_Verilog_HDL.ra DL : 0: Verilog是广泛应用的硬件描述语言，可以用在硬件设计流程的建模、综合和模拟等多个阶段。随着硬件设计规模的不断扩大，应用硬件描述语言进行描述的CPLD结构，成为设计专用集成电路和其他集成电路的主流。通过应用Verilog HDL对多功能电子钟的设计，达到对Verilog HDL的理解，同时对CPLD器件进行简要了解。本文的研究内容包括: 对Altera公司Flex 10K系列的EPF10K 10简要介绍，Altera公司软件Max+plusⅡ简要介绍和应用Verilog HDL对多功能电子钟进行设计。 -Verilog is the most widely used hardware description language.It can be used to the modeling, synthesis, and simulation stages of the hardware system design flow. With the scale of hardware design continually enlarging, describing the CPLD with HDL become the mainstream of designing ASIC and other IC.To comprehend Verilog HDL and get some knowledge of CPLD device, we design a block with several functions with Verilog HDL. This thesis is about to discuss the above there aspects: Introduce the EPF10K 10 of Flex 10K series producted by Altera Corporation simply. the software Max+plusⅡ,Design the block with several functions with Verilog HDL.
Date : 2025-12-23 Size : 471kb User : li
[VHDL-FPGA-Verilog] Max_PlusII_ppt DL : 0: Max+Plus II 的ppt文档，看后可以很轻易上手Max+Plus -Help
Date : 2025-12-23 Size : 1.62mb User : 李晓东
[VHDL-FPGA-Verilog] WATERHOURMETERBASEDONVHDL DL : 0: 在 MAX+PLUS II开发环境下采用 VHDL语言设计并实现了电表抄表器讨论了系统的四个组成模块的设计和 VHDL 的实现每个模块采用 RTL 级描述整体的生成采用图形输入法通过波形仿真下载芯片测试完成了抄表器的功能-In the MAX+ PLUS II development environment using VHDL language design and implementation of the meter meter reading device to discuss the four components of the system module design and VHDL implementation of each module using RTL-level description of a whole generation of graphical input waveform Simulation download chip testing completed meter reading functions
Date : 2025-12-23 Size : 234kb User : linfeng
[VHDL-FPGA-Verilog] MaxplusII DL : 0: 本电子书详细地介绍了VHDL语言开发环境 Max+plus II 软件的使用方法，让新手很快学会如何使用本软件-This book describes in detail VHDL language development environment Max+ plus II software to use, so that novices will soon learn how to use the software
Date : 2025-12-23 Size : 1mb User : may
[VHDL-FPGA-Verilog] max DL : 0: 这是一个在MAX+plus上面的计数器仿真图，基于FPGA的仿真。-This is a counter above the MAX+ plus simulation map, FPGA-based simulation.
Date : 2025-12-23 Size : 18kb User : 王天刚
[VHDL-FPGA-Verilog] fir-filter-design-using-fpga-with-MAX-Plus2 DL : 1: 基于FPGA的高阶FIR滤波器设计用max-plus　－II软件仿真-fir filter using fpga with max-plusII
Date : 2025-12-23 Size : 2.23mb User : 星空心晴之夏

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