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[VHDL-FPGA-Verilog] mdct.tar DL : 0: 这是06年4月刚刚完成的程序，从opencore.org下载而来。用vhdl语言描写，以及matlab仿真，testbench，以及在xinlinx上的综合。 The MDCT core is two dimensional discrete cosine transform implementation designed for use in compression systems like JPEG. Architecture is based on parallel distributed arithmetic with butterfly computation. -This is April 06 had just completed the process, from opencore.org downloaded from. Vhdl description language used, and Matlab simulation, testbench, and the Comprehensive xinlinx. The MDCT core is two dimensional discrete cosin e transform implementation designed for use in JPEG compression systems like. Architecture i 's based on parallel distributed arithmetic wit h butterfly computation.
Date : 2025-12-27 Size : 1.69mb User : 陈朋
[VHDL-FPGA-Verilog] miffile DL : 0: 用matlab产生mif文件。(Altera的EDA软件，如maxplus，quartus等用到的初始化rom，ram等的文件格式)-Mif files generated by matlab. (Altera' s EDA software, such as maxplus, quartus used to initialize and so on rom, ram, such as the file format)
Date : 2025-12-27 Size : 1kb User : 何亮
[VHDL-FPGA-Verilog] xb DL : 0: 用汉宁窗设计一个FIR高通数字滤波器，满足以下参数要求：通带边界频率ωp=0.7π，通带内衰减函数αp=0.4dB；阻带边界频率Ωs=0.4π，阻带内衰减函数为αs=55dB。-With the Hanning window design an FIR high-pass digital filter to meet the requirements the following parameters: passband edge frequency ωp = 0.7π, pass-band attenuation function αp = 0.4dB stop-band edge frequency Ωs = 0.4π, stop-band attenuation within the function αs = 55dB.
Date : 2025-12-27 Size : 123kb User : xbwu1
[VHDL-FPGA-Verilog] checkoutthedate DL : 0: 该程序的功能是用来查询日期或是知道日期查询星期几的；-The program' s function is used to check the date or the date of check to know a few of weeks
Date : 2025-12-27 Size : 2kb User : zhangcun
[VHDL-FPGA-Verilog] DDC_Ver1.0 DL : 0: 数字下变频（DDC）在如今基于软件无线电的架构中对系统的整体性能决定性的影响，代码为基于Matlab的4通道DDC程序，程序中可以根据需要调节滤波器等参数评估DDC的性能对于使用FPGA实现DDC有较大的参考价值-Digital down conversion (DDC) in today' s architecture based on software radio system a decisive impact on the overall performance of the code for the 4-channel DDC Matlab-based program, the program can be adjusted according to filter parameters such as the use of performance assessment FPGA DDC DDC has achieved great reference value
Date : 2025-12-27 Size : 2kb User : 易星
[VHDL-FPGA-Verilog] Wideband_DDC DL : 0: 宽带DDC的Verilog程序，及其MATLAB仿真程序看结果，最大可达100M带宽，程序中用的是50M-Wideband DDC' s Verilog program, and MATLAB simulation program to see the results, the maximum bandwidth of up to 100M, the program used is 50M
Date : 2025-12-27 Size : 8.08mb User : 左洪成
[VHDL-FPGA-Verilog] FPGA_study DL : 0: 特权同学的深入浅出玩转FPGA的PDF版，结合其自身实践经验以笔记的形式，讲述FPGA的学习非常适合初学者的使用。- the PDF version of FPGA, with author s own experience in the form of notes, to learn about the FPGA is very suitable for beginners to use.
Date : 2025-12-27 Size : 48.34mb User : 张昕
[VHDL-FPGA-Verilog] fir-and-iir DL : 0: FPGA关于数字滤波器设计,FIR的FPGA实现及其Quartus与MATLAB仿真-FPGA on the digital filter design, FIR s Quartus FPGA Implementation and Simulation with MATLAB
Date : 2025-12-27 Size : 4.91mb User : 方明
[VHDL-FPGA-Verilog] control DL : 1: 该程序描述了运用FPGA进行控制的S形曲线和其他传统加减速控制曲线方法的控制曲线比较研究。-This program is compiled in matlab circumstance。Describing the approach of S-curve control method in FPGA in machine controlling.
Date : 2025-12-27 Size : 780kb User : 赵九洲
[VHDL-FPGA-Verilog] DDS-Verilog-design-and-simulation DL : 0: DDS的Verilog设计及QuartusⅡ与Matlab联合仿真 -dds s verilog simulation dds s verilog simulation dds s verilog simulation dds s verilog simulation
Date : 2025-12-27 Size : 277kb User : 才一句
[VHDL-FPGA-Verilog] eulemethod DL : 0: Eules s method code - matlab
Date : 2025-12-27 Size : 1kb User : howyaaa
[VHDL-FPGA-Verilog] MATLAB-and-FPGA DL : 0: 以Xilinx公司的FPGA为开发平台，采用MATLAB及VHDL语言为开发工具，详细阐述数字通信同步技术的FPGA实现原理、结构、方法以及仿真测试过程-In Xilinx s FPGA development platform, using MATLAB and VHDL language development tools, elaborated synchronous digital communications technology FPGA implementation principles, structures, methods and process simulation test
Date : 2025-12-27 Size : 18.6mb User : C
[VHDL-FPGA-Verilog] TwoOderPll DL : 0: 1、资料包含二阶环路设计简要说明，Matlab程序，Matlab程序模拟FPGA工作方式，对各变量进行了量化处理 2、资料包含使用Vivado2015.4.2版本的工程文件，可直接运行查看仿真结果 3、参考资料为杜勇老师的《锁相环技术原理及其FPGA实现》(1. The data include a brief description of the second-order loop design. The MATLAB program and the MATLAB program simulate the working mode of the FPGA and quantify the variables. 2, the data contains Vivado2015.4.2 version of the engineering document, which can be run directly to see the simulation results. 3. Reference material is Du Yong's PLL technology principle and FPGA implementation.)
Date : 2025-12-27 Size : 31.04mb User : 三百钱
[VHDL-FPGA-Verilog] 好-无线通信FPGA设计-Xilinx DL : 1: 《无线通信FPGA设计》以Xilinx公司的FPGA开发平台为基础，综合FPGA和无线通信技术两个方向，通过大量的FPGA开发实例，较为详尽地描述了无线通信中常用模块的原理和实现流程，包括数字信号处理基础、数字滤波器、多速率信号处理、数字调制与解调、信道编码、系统同步、自适应滤波算法、最佳接收机，以及WCDMA系统的关键技术。《无线通信FPGA设计》概念明确、思路清晰，追求全面、系统、实用，使读者能够在较短的时间内具备无线通信领域的FPGA开发能力。(The design of wireless communication FPGA is based on the development platform of Xilinx's FPGA and combines the two directions of FPGA and wireless communication technology. Through a large number of examples of FPGA development, the principle and implementation process of common modules in wireless communication are described in detail, including the basis of digital signal processing, digital filter and multi-rate signal. Processing, digital modulation and demodulation, channel coding, system synchronization, adaptive filtering algorithm, optimal receiver, and key technologies of WCDMA system. The concept of Wireless Communication FPGA Design is clear, and the idea is clear. It pursues comprehensiveness, system and practicality, so that readers can have the ability to develop FPGA in the field of wireless communication in a relatively short time.)
Date : 2025-12-27 Size : 10.51mb User : 无线电之家99
[VHDL-FPGA-Verilog] 哈夫曼编码器设计实验报告 DL : 0: 要求对一段数据序列进行哈夫曼编码，使得平均码长最短，输出各元素编码和编码后的数据序列。 ①组成序列的元素是[0-9]这10个数字，每个数字其对应的4位二进制数表示。比如5对应0101，9对应1001。 ②输入数据序列的长度为256。 ③先输出每个元素的编码，然后输出数据序列对应的哈夫曼编码序列。(Design a 1MHz FIR low pass filter. Huffman coding is required for a section of data sequence to make the average code length the shortest, and the output of each element encoding and the encoded data sequence. The elements of the sequence are the 10 Numbers [0-9], each of which corresponds to a 4-bit binary representation. Let's say 5 is equal to 0101, and 9 is equal to 1001. The length of the input data sequence is 256. First output the encoding of each element, and then output the data sequence corresponding Huffman coding sequence. Requirements: (1) clock signal frequency 16MHz; (2) input signal bit width of 8bits, symbol rate of 16MHz Requirements in Matlab FIR filter floating-point and fixed-point simulation, and determine the FIR filter tap coefficient (4) write the test simulation program.)
Date : 2025-12-27 Size : 178kb User : 羊羊驼