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[VHDL-FPGA-Verilog] fftmatlab DL : 0: fft在dspbuilder下产生VHDL源码及其测试激励文件的matlab模型,在modelsim下仿真通过-fft in dspbuilder under VHDL source code and test incentives document matl ab model, the simulation under through modelsim
Date : 2025-12-24 Size : 7kb User : zqh
[VHDL-FPGA-Verilog] Fibonacci_sequence DL : 0: 用MATLAB 里的XILINX BLOCKS编写, 实现Fibonacci sequence算法, 当F为0时, 输出为0 F为1时, 输出为1 当F为N 时, 输出为F的N-1 加上 F的N-2.-Using MATLAB in the XILINX BLOCKS prepared realize Fibonacci sequence algorithm, when F is 0, the output for 0 F for one, the output is 1 when F is N, the output for the F of the N-1 plus F of N-2 .
Date : 2025-12-24 Size : 25kb User : zhang tian
[VHDL-FPGA-Verilog] FSK_work DL : 0: 自己做的基于MATLAB DSP BUILDER的FSK,里面的内容都在，整个工程-MY FSK,have cost much time。please use it carefully。
Date : 2025-12-24 Size : 697kb User : 朱铭进
[VHDL-FPGA-Verilog] reload_fir DL : 0: 这是我在Xilinx公司的FPGA上实现的FIR滤波器，调用的内部核，其特色是可以用较少的资源实现该功能，而且可以实现参数重载，即从外部MCU设置FIR滤波器的参数-This is my Xilinx FPGA to achieve the FIR filter, called internal audit, its characteristics can be achieved with fewer resources to this function, and the overload parameters can be achieved, that is, from an external MCU to set the parameters of FIR Filter
Date : 2025-12-24 Size : 15.95mb User : 林寒风