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[VHDL-FPGA-Verilog] 数字锁相环 DL : 0: PLL是数字锁相环设计源程序, 其中, Fi是输入频率(接收数据), Fo(Q5)是本地输出频率. 目的是从输入数据中提取时钟信号(Q5), 其频率与数据速率一致, 时钟上升沿锁定在数据的上升和下降沿上；顶层文件是PLL.GDF-digital phase-locked loop PLL design source, in which Fi is the input frequency (receive data), Fo (Q5) is the local output frequency. Objective is to extract data input clock signal (Q5), its frequency and data rate line, the clock rising edge of the lock data the rising and falling edge; top-level document is PLL.GDF
Date : 2025-12-21 Size : 122kb User : 于洪彪
[VHDL-FPGA-Verilog] a DL : 0: ADPLL of high level phase locked loop
Date : 2025-12-21 Size : 1.4mb User : bc
[VHDL-FPGA-Verilog] mydesign DL : 0: 基于FPGA的直接序列扩频发射机的设计与仿真。实验中以QuartusII 7.2 为设计和仿真工具，各模块采用Verilog HDL设计并封装，顶层使用图形设计方式,最后得到的仿真结果使用Matlab描点来绘制出波形。 -FPGA-based direct sequence spread spectrum transmitter of the design and simulation. Experiment to QuartusII 7.2 for the design and simulation tools, the module using Verilog HDL to design and package, the top-level use of graphic design, and finally the simulation results obtained using the Matlab description points to draw waveforms.
Date : 2025-12-21 Size : 352kb User : fengjianhui
[VHDL-FPGA-Verilog] gvnpp DL : 0: Contains two clients receive link-level communications program, Based on wavelet transform digital watermarking algorithm matlab code, LCMV optimization design array signal processing.
Date : 2025-12-21 Size : 4kb User : fangfielingfai
[VHDL-FPGA-Verilog] sb133 DL : 0: Based on SVPWM three-level inverter matlab simulation, It describes the application of load forecasting, EULER numerical analysis method.
Date : 2025-12-21 Size : 10kb User : leijuiyiuhan
[VHDL-FPGA-Verilog] nfqud DL : 0: Using MATLAB dynamic clustering or iterative self-organizing data analysis, The performance of the program has reached a high level, MinkowskiMethod algorithm.
Date : 2025-12-21 Size : 7kb User : tyasiu
[VHDL-FPGA-Verilog] 信号分析与处理——MATLAB语.part1 DL : 0: ① Verilog的抽象级别 ② Verilog的模块化设计 ③ 如何给端口选择正确的数据类型 ④ Verilog语言中latch的产生 ⑤ 组合逻辑反馈环 ⑥ 阻塞赋值与非阻塞赋值的不同 ⑦ FPGA的灵魂状态机 ⑧ 代码风格的重要性((1) the abstract level of Verilog The modular design of Verilog How to select the correct data type for the port (4) the generation of latch in Verilog language Combinational logic feedback loop The blocking and nonblocking assignment assignment different The soul of state machine FPGA The importance of the code style)
Date : 2025-12-21 Size : 1.39mb User : mmelody