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[VHDL-FPGA-Verilog] czcgl DL : 0: 出租车管理系统,为本人毕业设计. 还请大家多多指教了-Taxi management system, for my graduation project. Also requests the exhibitions of the U.S.
Date : 2025-12-18 Size : 2.11mb User : wyqfhls
[VHDL-FPGA-Verilog] SSMS DL : 0: 汇编实习作业汇编语言实现的学生信息管理系统-Compilation of assembly language to achieve practical operation of Student Information Management System
Date : 2025-12-18 Size : 2kb User : 刘海
[VHDL-FPGA-Verilog] baseonFPGA DL : 0: 实时电话计费系统是企业、事业单位信息管理的一个重要组成部分。介绍了一种用FPGA 器件实现电话计费系统的方法, 并给出了设计框图和详细设计过程, 设计采用Verilog_HDL 硬件语言。-Real-time telephone billing system is the enterprise information management institutions as an important component. Introduction of a FPGA device using telephone billing system methods, and gives the design diagram and detailed design process, design hardware Verilog_HDL language.
Date : 2025-12-18 Size : 519kb User : daifuxin
[VHDL-FPGA-Verilog] guide DL : 0: 华为_大规模逻辑设计指导书，看看人家是怎么管理FPGA编程的，真的获益匪浅-Huawei _ large-scale logic design guide book, take a look at how the management of people FPGA programming, and really benefited from
Date : 2025-12-18 Size : 1.95mb User : xiaoyuer
[VHDL-FPGA-Verilog] Ring_mem_VHDL DL : 0: 响铃和内存管理功能的VHDL语言，用于程控交换机中的Xillinx芯片与DSP和ADDA等芯片配合实现交换机的功能-Ringing and memory management features VHDL language, for program-controlled switchboards in Xillinx and ADDA chip and DSP chip, etc. with the function of switches realize
Date : 2025-12-18 Size : 12kb User : alanwater
[VHDL-FPGA-Verilog] mdio-md DL : 1: 目前以太网PHY芯片是通过总线MDC/MDIO，但是基本上是通过MAC芯片直接管理的，本代码实现了通过FPGA管理PHY。即由FPGA完成MII管理-At present, Ethernet PHY chip through the bus MDC/MDIO, but basically through the direct management of MAC chip, the code through the FPGA implementation management PHY. FPGA completed by the MII management
Date : 2025-12-18 Size : 2kb User : leon
[VHDL-FPGA-Verilog] pld DL : 0: 四字路口交通灯管理器的设计（含波形输出）-Management of traffic lights at the junction word design (including waveform output)
Date : 2025-12-18 Size : 107kb User : 庞永亮
[VHDL-FPGA-Verilog] SF_table_interface DL : 0: switch fabric部分代码: fabric和table management 的数据交换. Mac address 从afifo输入, 查询的结果:output port number 存于pfifo中-switch fabric part of the code: fabric and table management data exchange. Mac address from afifo input, the results of inquiries: output port number stored in Medium pfifo
Date : 2025-12-18 Size : 2kb User : 无影
[VHDL-FPGA-Verilog] Fingerprint_Identify DL : 0: 本项目名称是：基于FPGA的指纹识别模块设计。主要内容为：本模块采用xilinx公司的Spartan 3E系列XC3S500E 型FPGA作为核心控制芯片，通过富士通公司的MFS300滑动式电容指纹传感器对指纹图象进行提取，然后对提取的指纹图像进行灰度滤波、图像增强、二值化、二值去噪、细化等预处理，得到清晰的指纹图象，再从清晰的指纹图象中提取指纹特征点，存入外部FLASH作为建档模板。指纹比对时，采用同样的方法获得清晰的指纹图像，建立比对模板，然后将比对模板与建档模板利用点模式匹配算法进行比对，得出比对结果。该模块利用嵌入式软核实现系统的管理，利用硬件实现指纹识别，保证了系统功能的完整性与识别的正确性。该识别模块可用于门禁、考勤、安检、保险箱柜等很多方面，也可和计算机等设备联机使用，满足各个方面的不同需求，因此它的设计具有很广泛的应用前景和市场价值。 -The project name is: FPGA-based fingerprint identification module design. The main contents are: the use of this module xilinx s Spartan 3E Series XC3S500E FPGA-based control chip as the core, through the MFS300 Fujitsu fingerprint slide sensor capacitance extraction of the fingerprint image, and then extracted gray-scale fingerprint image filtering, image enhancement, binarization, denoising Second, refinement, etc. pre-treatment have been given clear fingerprint image, and then a clear fingerprint image from the extracted fingerprint feature points, into the external FLASH file as a template. Fingerprint matching using the same method to obtain a clear image of the fingerprint to establish than the template, and then will be the template file templates and the use of point pattern matching algorithm than the right, than the results obtained. The module is the realization of the use of soft-core embedded system management, the use of fingerprint recognition hardware implementation
Date : 2025-12-18 Size : 187kb User : xiaoxu
[VHDL-FPGA-Verilog] TaxiManagementSystem DL : 0: 一个出租车管理程序，适合新手，vc编辑，打开就可以用-A taxi management procedures suitable for novice, vc Editor
Date : 2025-12-18 Size : 563kb User : 程然
[VHDL-FPGA-Verilog] ESIMERKKISOVELLUS_V13 DL : 0: Actel Fusion System Management Kit Libero Design for using I2C
Date : 2025-12-18 Size : 47.84mb User : LoomVortex
[VHDL-FPGA-Verilog] FPGA_note DL : 0: 这主要是在学习FPGA设计过程中的笔记.主要是：FPGA设计中的电源管理，关键问题，PLDFPGA结构与原理初步的认识，以及如何养成良好的编程习惯、大型设计中FPGA的多时钟设计策略及其概念：毛刺、竞争、冒险。-This is mainly to learn FPGA design process in the notes. Is mainly: FPGA design, power management, the key question, PLDFPGA preliminary understanding of the structure and principles, and how to develop good programming habits, large-scale design of multi-FPGA clock design strategy and concept: the burr, competition, adventure.
Date : 2025-12-18 Size : 756kb User : hwei
[VHDL-FPGA-Verilog] CyclonePLL DL : 0: Cyclone™ FPGA具有锁相环（PLL）和全局时钟网络，提供完整的时钟管理方案。Cyclone PLL具有时钟倍频和分频、相位偏移、可编程占空比和外部时钟输出，进行系统级的时钟管理和偏移控制。Altera® Quartus® II软件无需任何外部器件，就可以启用Cyclone PLL和相关功能。本文将介绍如何设计和使用Cyclone PLL功能。 PLL常用于同步内部器件时钟和外部时钟，使内部工作的时钟频率比外部时钟更高，时钟延迟和时钟偏移最小，减小或调整时钟到输出（TCO）和建立（TSU）时间。 -Cyclone ™ FPGA with a phase-locked loop (PLL) and the global clock network and provide a complete clock management solution. Cyclone PLL with the clock multiplier and divider, phase offset, programmable duty cycle and the external clock output for system-level clock management and offset control. Altera ® Quartus ® II software does not require any external devices, you can enable the Cyclone PLL and related functions. This article describes how to design and use the Cyclone PLL features. PLL clock devices commonly used in the synchronization of internal and external clock, so that the inner workings of the clock frequency higher than the external clock, clock delay and clock skew minimum, reduce or adjust the clock to the output (TCO) and the establishment of (TSU) time.
Date : 2025-12-18 Size : 541kb User : 裴雷
[VHDL-FPGA-Verilog] FPGA_CPLD_Design_Tools_Xilinx_ISE_5_X_use_Xiangjie DL : 0: 本书以FPGA/CPLD设计流程为主线，阐述了如何合理利用ISE设计平台集成的各种设计工具，高效地完成FPGA/CPLD的设计方法与技巧。全书在介绍FPGA/CPLD概念和设计流程的基础上，依次论述工程管理与设计输入、仿真、综合、约束、实现与布局布线、配置调试等主要设计步骤在ISE集成环境中的实现方法与技巧。本书立足工程实践，结合作者多年工作经验，选用大量典型实例，并配有一定数量的练习题。本书配套光盘收录了所有实例的完整工程目录、源代码、详细操作步骤和使用说明，利于读者边学边练，提高实际应用能力。本书可作为高等院校通信工程、电子工程、计算机、微电子与半导体学等专业的教材，也可作为硬件工程师和IC工程师的实用工具书。 -The book FPGA/CPLD design flow as the main line, explains how the rational use of ISE design platform integrates a variety of design tools and efficient completion of FPGA/CPLD design methods and techniques. In introducing the book FPGA/CPLD concept and design process, based on the order discussed in project management and design entry, simulation, synthesis, constraints, implementation and layout routing, configuration, debugging and other major steps in the ISE design environment, the realization of an integrated approach and techniques. This book based on engineering practice, combined with the author many years of work experience, use a large number of typical examples, and is equipped with a number of exercises. This book package CD-ROM contains all the instances of a complete project directory, source code, detailed steps and instructions for use, which will help the reader to learn while training to improve the practical application ability. This book can serve as institutio
Date : 2025-12-18 Size : 33.33mb User : cai
[VHDL-FPGA-Verilog] AD5320BRM DL : 0: Management DAC AD5320BRM (for NIOS2)
Date : 2025-12-18 Size : 1kb User : sergey
[VHDL-FPGA-Verilog] ADF4106 DL : 0: Management of synthesizer ADF4106
Date : 2025-12-18 Size : 1kb User : sergey
[VHDL-FPGA-Verilog] memtest DL : 0: 在数字系统中，一般存在多个芯片，利用不同的特点用于实现不同的功能，一般都包含CPU,FPGA,AD,DA,memory，ASSP（专用标准模块）,ASIC等。CPU用于进行智能控制，FPGA进行硬件算法处理和多设备接口，AD进行模数转换，DA进行数模转换，memory存储临时数据。因此，FPGA如何与其他芯片进行通讯是重要的设计内容。数据输入，数据输出，双向通讯，指令传递，地址管理，不同时钟的异步通讯问题等等都需要处理。最基本的MEMORY如SRAM(128KX8bbit静态存储器628128)涉及到其中的输入，输出，双向通讯，地址管理问题，具有很强的代表性。在同步数字系统中更大量用到FIFO,SDRAM等等。其中FIFO使用方便简单，用处很广。在QUARTUSII软件库中，就有各种FPGA片内MEMORY供使用。但是FPGA的片内MEMORY容量太有限，因此外部MEMORY也是经常需要的。因此，本程序让大家学习控制芯片内外的MEMORY,为与其他智能设备的通讯学习打下基础。-In the digital system, generally there are several chips, the use of different features used to implement different functions, generally includes CPU, FPGA, AD, DA, memory, ASSP (application specific standard module), ASIC and so on. CPU is used for intelligent control, FPGA hardware algorithm processing and multi-device interface, AD to ADC, DA for digital-analog conversion, memory to store temporary data. Therefore, FPGA how to communicate with other chips are important design elements. Data input, data output, two-way communication, instruction delivery, address management, different clock asynchronous communication problems, and so have to deal with. If the most basic MEMORY SRAM (128KX8bbit static memory 628 128) which involved the input, output, bi-directional communication, address management issues, with strong representation. In synchronous digital systems a lot more use FIFO, SDRAM, etc.. One simple and easy to use FIFO, use very broad. In QUARTUSII software library, there ar
Date : 2025-12-18 Size : 218kb User : 平凡
[VHDL-FPGA-Verilog] synplify_makefile DL : 0: synplify、ise和verdi在linux上的makefile；多个工具集成在一个文件管理，方便快捷，值得参考-the makefile for synplify, ise and verdi on Linux multiple tools integrated into a document management, convenient and valuable reference! ! !
Date : 2025-12-18 Size : 1kb User : Jasking Wu
[VHDL-FPGA-Verilog] Xilinx_Altera_FPGAs DL : 0: Xilinx和Altera FPGAs的电源管理解决方案-Xilinx 和 Altera FPGAs power management solutions
Date : 2025-12-18 Size : 698kb User : hwd
[VHDL-FPGA-Verilog] FPGA DL : 0: 在该文档中详细介绍了如何用FPGA语言对电梯进行群控管理。-In the document describes in detail how to use FPGA language elevator group control management.
Date : 2025-12-18 Size : 7mb User : wangbaohua

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