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[VHDL-FPGA-Verilog] TrafficLight DL : 0: 通过硬件描述语言VHDL编程，实现交通灯功能，要求如下：　　① 车辆传感器（C），检测车辆通行情况，用于主干道的优先权控制； ② 主干道公路路口安装有人员通过请求按钮（PQ），一旦有请求信息，控制器应按放行处理，否则按默认方式处理； ③ Online控制信号由交通控制中心发出，（Online=1）一旦它有效，则主干道放行，十字交叉路口控制器“失效”，Online=0十字交叉路口控制器恢复控制权；　　④ 当次干道公路无车时，始终保持次干道公路红灯亮，主干道绿灯亮； ⑤ 当次干道公路有车时，而主干道通车时间已经超过它的最短通车时间时，禁止主干道通行，让次干道公路通行。主干道最短通车时间为25s ； ⑥ 当次干道公路和主干道都有车时，按主干道通车25s，次干道公路通车16s交替进行；　　⑦ 不论主干道情况如何，次干道公路通车最长时间为16s； ⑧ 在每次由绿灯亮变成红灯亮的转换过程中，要亮5s时间的黄灯作为过渡； ⑨ 用两组开关代替传感器作为检测人员通过请求和车辆是否到来的信号。用红、绿、黄三种颜色的发光二极管作交通灯；　　⑩ 要求显示时间，倒计时。-Through hardware description language VHDL programming, traffic lights functional requirements are as follows: ① vehicle sensors (C), detection of vehicle traffic situation, the priority control for the main road ② trunk road junctions equipped with staff through a request button (PQ), if there is a request message, the controller should be released, otherwise handled by default ③ Online control signal issued by the traffic control center, (Online = 1) if it is valid, trunk release, cross the intersection Controller "failure", Online = 0 crossroad controller resumes control over ④ When the secondary trunk road no car, and always maintain secondary roads road red light, green light main road ⑤ When the secondary trunk road with the car, while the trunk opening time has exceeded its minimum opening time, prohibited roads impassable, so that secondary roads roads impassable. Trunk shortest time for the opening 25s ⑥ When the sub-trunk roads and main roads have vehicle, accordin
Date : 2025-12-19 Size : 8.51mb User : 韩彩英
[VHDL-FPGA-Verilog] Codes DL : 0: USB 2.0 using VHDL with files : main.c, drice.c and HIGH_SPEED_USB_CORE_SETUP_TRANSACTION
Date : 2025-12-19 Size : 56kb User : altenategoody
[VHDL-FPGA-Verilog] LIBRARY DL : 0: 交通信号灯 (1)、设计一个南北方向为主干道，东西方向为支干道的； (2)、选择一个标准时钟发生电路，为电路提供一个标准1HZ信号； (3)、(a)交通灯从绿变红时，有5秒黄灯亮的间隔时间；(b)交通灯红变绿是直接进行的，没有间隔时间；(c)主干道上的绿灯时间为50秒，支干道的绿灯时间为30秒(traffic light Design a north-south direction of the main road, East and west direction for the trunk road;)
Date : 2025-12-19 Size : 13kb User : godlu666
[VHDL-FPGA-Verilog] C51 DL : 0: 基于5-1单片机环境噪声测量仪的设计，包含主程序、中断服务程序、显示程序、(Based on 51 single-chip environmental noise detector proteus simulation file containing a set of project files noise.dsn Keil main code main.c 6 relevant articles and graduation thesis design through simulation)
Date : 2025-12-19 Size : 2kb User : 哈哈哈哈3