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[VHDL-FPGA-Verilog] 数字锁相环 DL : 0: PLL是数字锁相环设计源程序, 其中, Fi是输入频率(接收数据), Fo(Q5)是本地输出频率. 目的是从输入数据中提取时钟信号(Q5), 其频率与数据速率一致, 时钟上升沿锁定在数据的上升和下降沿上；顶层文件是PLL.GDF-digital phase-locked loop PLL design source, in which Fi is the input frequency (receive data), Fo (Q5) is the local output frequency. Objective is to extract data input clock signal (Q5), its frequency and data rate line, the clock rising edge of the lock data the rising and falling edge; top-level document is PLL.GDF
Date : 2026-01-11 Size : 122kb User : 于洪彪
[VHDL-FPGA-Verilog] password_lock DL : 0: 这是使用VHDL语言编写的密码锁程序,供大家参考-This is the use of the VHDL code lock preparation procedures for reference
Date : 2026-01-11 Size : 301kb User : 黄鹏飞
[VHDL-FPGA-Verilog] 7064 DL : 0: vhdl代码写的一个密码锁程序，用EPM7064SLC44-10就可以实现-vhdl code written in a code lock procedures used EPM7064SLC44-10 can be achieved
Date : 2026-01-11 Size : 117kb User : w w w
[VHDL-FPGA-Verilog] elec_lock DL : 0: 本程序是用VHDL语言实现电子密码锁功能,整个系统分为三大模块,一为控制模块,二为键盘显示模块,三为处理模块-This procedure is a VHDL language electronic code lock function, the entire system is divided into three modules, one for the control module, two for the keyboard display module, three modules for the treatment
Date : 2026-01-11 Size : 263kb User : 敬礼
[VHDL-FPGA-Verilog] lock DL : 0: 这个是我毕业设计的最初方案 8位二进制密码锁，在输入密码正确的情况下修改密码，显示输入密码，正确显示绿灯提示，错误显示红灯提示并报警。-This is my graduate program was originally designed eight binary code lock in the correct password to modify your password, enter the password shows the correct green tips, error display and alarm red tips.
Date : 2026-01-11 Size : 91kb User : 孙光华
[VHDL-FPGA-Verilog] mimasuo DL : 0: 用VHDL编写的数字密码锁,很实用，喜欢请下载-Prepared using VHDL digital code lock, it is practical, likes to download
Date : 2026-01-11 Size : 2kb User : ding
[VHDL-FPGA-Verilog] LOCK DL : 0: 以QuatusⅡ为平台，采用VHDL语言实现数字密码锁的功能，可以仿真实现。-To Quatus Ⅱ as a platform, the use of VHDL language digital code lock function, you can realize simulation.
Date : 2026-01-11 Size : 183kb User : cheng sonja
[VHDL-FPGA-Verilog] vhdl DL : 0: 基于EDA技术的数字密码锁源程序代码,大学实训用的着-EDA-based Digital code lock source code, used by the University Training
Date : 2026-01-11 Size : 7kb User : shark
[VHDL-FPGA-Verilog] lock DL : 0: 功能： 1、密码输入：每按下一个键，要求在数码管上显示，并依次左移； 2、密码清除：清除密码输入，并将输入置为”0000”； 3、密码修改：将当前输入设为新的密码； 4、上锁和开锁。-Features: 1, enter the password: press a key for each request in the digital tube display, and turn left 2, password clear: to remove the password input, and will enter the home as 0000 3, password modification: the current Enter the new password set 4, lock and unlock.
Date : 2026-01-11 Size : 151kb User : 谢柳
[VHDL-FPGA-Verilog] vhdl4 DL : 0: 数字密码锁： 1.系统具有预置的初始密码“00000001”。 2.输入密码与预存密码相同时，开锁成功，显示绿灯，否则开锁失败，显示红灯。 3.具有修改密码功能。修改密码时，先开锁，开锁成功才可以修改。 4.系统同时具有关锁功能。关锁后，显示红灯。 5.密码由拔码开关表示，开锁由按键表示。 6具有一个复位按键。按键后，回到初始状态。 -The number of locks: 1. System has preset the initial password 00000001. 2. Enter the password with the stored password is the same, unlock success, showing a green light, or else unlock the failure to show a red light. 3. With the Change Password function. Modify password, to unlock, unlock success only can be amended. 4. System lock clearance at the same time. Clearance after the lock, showing a red light. 5. Password code switch from Stubbs said that by the keys that unlock. 6 has a reset button. Button to return to the initial state.
Date : 2026-01-11 Size : 246kb User : 宫逢源
[VHDL-FPGA-Verilog] ElectronicCodeLock DL : 0: 设计一个通用电子密码锁，具体功能如下：[1]数码输入 [2]数码清除 [3]密码更改 [4]激活电锁 [5]解除电锁-The design of a universal electronic code lock, the specific features are as follows: [1] digital input [2] Digital Clear [3] Password Change [4] to activate electric lock [5] the lifting of electric locks
Date : 2026-01-11 Size : 1kb User : 小夏
[VHDL-FPGA-Verilog] Electronic_combination_lock DL : 0: 实现电子密码锁的功能，有密码出错，修改密码等功能-Electronic combination lock
Date : 2026-01-11 Size : 467kb User :
[VHDL-FPGA-Verilog] CodeLock DL : 0: 用于模仿密码锁的工作过程。完成密码锁的核心控制功能。可实现数码输入、清除、退位、设置密码、错误提示、系统报警、解除报警、系统关闭等功能。-Used to imitate the work of the code lock process. Locks achieve the core control functions. Digital input can be achieved, clear, step down, set a password, error message, the system alarm, lift the alarm, turn off the functions of the system.
Date : 2026-01-11 Size : 13kb User : 胡婕
[VHDL-FPGA-Verilog] PLL DL : 0: PLL是数字锁相环设计源程序, 其中, Fi是输入频率(接收数据), Fo(Q5)是本地输出频率. 目的是从输入数据中提取时钟信号(Q5), 其频率与数据速率一致, 时钟上升沿锁定在数据的上升和下降沿上；顶层文件是PLL.GDF-Digital phase-locked loop PLL is the design source code, which, Fi is the input frequency (receive data), Fo (Q5) is a local output frequency. The purpose is to extract data from the input clock signal (Q5), their frequency and data rate in line clock rising edge of lock-in data on rising and falling edge PLL.GDF top-level document
Date : 2026-01-11 Size : 124kb User : 许伟
[VHDL-FPGA-Verilog] digital_lock DL : 0: Verilog code for digital combinational lock //BCAC – Unlock sequence //wrong sequence –alaram goes on and goes off only after pressin another 4 wrong buttons. //once the lock is open ,we can close the lock by pressin any key //From any state pressin AA gets back to reset state.-Verilog code for digital combinational lock //BCAC – Unlock sequence //wrong sequence –alaram goes on and goes off only after pressin another 4 wrong buttons. //once the lock is open ,we can close the lock by pressin any key //From any state pressin AA gets back to reset state.
Date : 2026-01-11 Size : 7kb User : deepa
[VHDL-FPGA-Verilog] Lock DL : 0: 密码锁，本设计是根据小区的门，来设计的。这个设计，可以减少一个保安，什么的。具有使用价值。-Lock, the design is based on cell doors, to design. This design can reduce a security, or something. Has a value.
Date : 2026-01-11 Size : 1.14mb User : 红儿
[VHDL-FPGA-Verilog] lock DL : 0: 设计一个8位串行数字密码锁控制电路 -Design an 8-bit serial digital code lock control circuit
Date : 2026-01-11 Size : 1kb User : 冷与
[VHDL-FPGA-Verilog] VHDL_digital_lock_design DL : 0: VHDL课程的源代码数字密码锁的设计与实现的实验报告，内附源代码-VHDL source code for the course digital code lock design and implementation of the experimental report, included the source code
Date : 2026-01-11 Size : 4kb User : CXJ
[VHDL-FPGA-Verilog] VHDL(LOCK) DL : 0: 数字密码锁的设计与实现一．实验目的 1. 学习VHDL的综合设计应用 2. 学习数字密码锁的设计二．实验内容设计一个数字密码锁，对其编译，仿真，下载。数字密码锁具体要求如下： 1.系统具有预置的初始密码“00000001”。 2.输入密码与预存密码相同时，开锁成功，显示绿灯，否则开锁失败，显示红灯。 3.具有修改密码功能。修改密码时，先开锁，开锁成功才可以修改。 4.系统同时具有关锁功能。关锁后，显示红灯。 5.密码由拔码开关表示，开锁由按键表示。 6具有一个复位按键。按键后，回到初始状态。 -VHDL Digital Design and Implementation of lock 1. Purpose of the experiment 1. VHDL Integrated Design and Application of Learning 2. Learning digital code lock design 2. Experimental content Design a digital lock on their compilation, simulation, download. Digital code lock specific requirements are as follows: 1. System has preset the initial password "00000001." 2. Enter the same password with the stored password, unlock successful, a green light, or unlock failed to show a red light. 3. With the change password function. Modify password, the first lock, unlock success can modify. 4. The system also has off lock. Shut up after the red light. 5. The password code from the pull switch that unlock the keys, said. 6 has a reset button. Button, the return to initial state.
Date : 2026-01-11 Size : 18kb User : 爱好
[VHDL-FPGA-Verilog] digital-lock DL : 0: 电子密码锁功能如下: l、按键接口的设计包括： 1）键盘扫描电路 2）弹跳消除电路 3）键盘译码电路 4）按键存储电路 2、密码锁的控制电路设计包括： 1）按键的数字输入、存储及清除 2）功能按键的功能设计 3）移位寄存器的设计与控制 4）密码清除、变更、存储、激活电锁电路 5）密码核对、解除电锁电路 3、输出七段显示电路的设计包括： 1）数据选择电路 2）BCD对七段显示译码电路 3）七段显示扫描电路密码锁功能说明： 1、数据输入：每按一个数字键，就输入一个数值，并在显示器上的最右方显示出该数值，并将先前已经输入的数据依序左移一个数字位置。 2、数码清除：按下此键可清除前面所有的输入值，清除成为“0000”。 3、密码更改：按下此键时将日前的数字设定成新的密码。 4、激活电锁：按下此键可将密码锁上锁。 5、解除电锁：按下此键会检查输入的密码是否正确，密码正确即开锁。 -Electronic locks l, key interface design Include: 1) The keyboard scanning circuit 2) bounce elimination circuit 3) Keyboard decoding circuit 4) The button memory circuit 2, the lock control circuit design Include: 1) Press the digital input, storage and removal 2) The functional design of function keys 3) Design and Control of the shift register 4) remove the password, change, storage, activate the electric lock circuit 5) The password check, the lifting power lock circuit 3, the output of seven-segment display circuit Include: 1) data selection circuit 2) BCD seven segment display decoder circuit of 3) seven segment display scanning circuit Password Lock Function: 1, the data entry: Each press a number key to enter a value, and in the far right on the display shows the number and order of input data previously left a number of locations. 2, Digital Clear: Press this key to clear all previous input values , clear
Date : 2026-01-11 Size : 127kb User : ldong1989

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