Search - lms algorithm

Search - lms algorithm - List

[VHDL-FPGA-Verilog] FPGA_LMS DL : 1: VHDL写的LMS算法程序。利用本地正弦信号，根据LMS算法对输入信号进行跟踪。用以产生和输入信号同频同相的本地信号。-VHDL LMS algorithm written procedures. The use of local sinusoidal signal, according to the LMS algorithm for tracking the input signal. Used to produce and the input signal with frequency phase with the local signal.
Date : 2026-01-01 Size : 264kb User : 黄鹤
[VHDL-FPGA-Verilog] ante DL : 0: 智能天线自适应LMS算法，假设具有4个天线阵元。-Smart antenna adaptive LMS algorithm, the assumption that with four million antenna array.
Date : 2026-01-01 Size : 4kb User : 黄虎
[VHDL-FPGA-Verilog] adaptive_lms_equalizer_latest.tar DL : 0: In communication systems channel poses an important role. channels can convolve many different kind of distortions to our information. In perticular wireless channels multipath distortion is sevear. and more sevear is such distortion is random. To handle this, multipath affected channels require Equalizers at receaver end. such equalizer uses different learning Algorithms for identifying channels continuously. This project is VHDL implementation of LMS learning algorithm with pipelined architecture. so this implementation can work with higher data rates with less clock speed requirments and so with less power consumpiton It uses Fixed point arithmatic blocks for filtering so suitable for coustom asic.
Date : 2026-01-01 Size : 14kb User : Arun
[VHDL-FPGA-Verilog] AdaptiveLMSequalizer DL : 0: 通信中的用的LMS均衡算法VHDL实现，代码不长，很容易看懂-Communication with the LMS equalization algorithm to achieve VHDL code is not long, it is easy to understand
Date : 2026-01-01 Size : 3kb User : 王王
[VHDL-FPGA-Verilog] lms DL : 0: 一个不错的关于lms算法的verilog代码，算然只有两级，但是对了解lms用HDL描述有很好的理解作用。希望对大家有用~-A good lms algorithm on the verilog code, development environment, I can not find, even if the vhdl it! We hope to be useful
Date : 2026-01-01 Size : 1kb User : onion
[VHDL-FPGA-Verilog] fir_lms DL : 0: 一个不错的关于lms算法的verilog代码，算然只有两级，但是对了解lms用HDL描述有很好的理解作用。希望对大家有用~-A good lms algorithm on the verilog code, development environment, I can not find, even if the vhdl it! We hope to be useful
Date : 2026-01-01 Size : 1kb User : onion
[VHDL-FPGA-Verilog] HDLImplementationoftheVariableStepSize DL : 0: proposes a Verilog implementation of the Normalized Least Mean Square (NLMS) adaptive algorithm, having a variable step size. The envisaged application is the identification of an unknown system. First the convergence of derived LMS algorithms was analyzed in a Simulink application.
Date : 2026-01-01 Size : 218kb User : 陳柏宇
[VHDL-FPGA-Verilog] rs232 DL : 0: FPGA 数字滤波算法资料，自己可以设计等LMS 算法-FPGA Digital Filter Algorithm for information, they can design LMS algorithm
Date : 2026-01-01 Size : 58kb User : suupy
[VHDL-FPGA-Verilog] ERROR_COUNTING_BLOCK DL : 0: vhdl code for error counting blk in lms algorithm
Date : 2026-01-01 Size : 5kb User : lekshmi
[VHDL-FPGA-Verilog] WEIGHT_UPDATE_BLOCK DL : 0: weight updateblock of lms algorithm
Date : 2026-01-01 Size : 5kb User : lekshmi
[VHDL-FPGA-Verilog] fir_lms DL : 0: finite impulse response LMS algorithm verilog code
Date : 2026-01-01 Size : 36kb User : zcos123
[VHDL-FPGA-Verilog] lmsFPGA DL : 0: 利用VHDL编程实现自适应滤波算法的程序，实现LMS算法-VHDL programming procedures for adaptive filtering algorithms, the LMS algorithm
Date : 2026-01-01 Size : 8kb User : 朱岩
[VHDL-FPGA-Verilog] vhdl_lms DL : 0: vhdl 语言实现的lms算法的自适应滤波器两种实现方式包括改进-VHDL language lms algorithm adaptive filter implemented in two ways including improved
Date : 2026-01-01 Size : 45kb User : zhanshen
[VHDL-FPGA-Verilog] lms DL : 1: 文件中为lms算法的ise工程，其中包含了lms算法的fpga实现的verilog程序以及testbench，很好的在FPGA上实现了lms算法，还有一些调试程序的总结-Ise project file for lms algorithm, which contains the lms algorithm fpga verilog program to achieve and testbench good lms algorithm implemented on FPGA debugger summary
Date : 2026-01-01 Size : 2.68mb User : 黄远望
[VHDL-FPGA-Verilog] LMS_algorithm_matlab DL : 0: 此matlab代码介绍了LMS（leastMeansquare）的算法实现，具有很好的参考价值-LMS algorithm in adaptive algorithm using a very wide range. Reversal of the traditional the offset algorithm that using this algorithm. This matlab code program great reference significance of the adaptive algorithm design
Date : 2026-01-01 Size : 1kb User : brianwu
[VHDL-FPGA-Verilog] ifir_64 DL : 0: verilog hdl, quartus.64阶的简单回声抵消器，采用的是基本的LMS算法，简单改进，可用于初期了解。功能背景是对通信领域中，比如打电话时自己的声音到达对方经对方环境多径反射又传回自己这边，即回声。为将回声消除采用回声抵消装置。-64 steps a simple echo canceller is used in the basic LMS algorithm, a simple improvement, can be used for the initial understanding. Functional background in the field of communication, such as a call to reach the other environmental multipath reflections after each other and return to their side, that echo of their own voice. To echo cancellation echo cancellation device.
Date : 2026-01-01 Size : 38.38mb User : yy
[VHDL-FPGA-Verilog] LMS DL : 0: 用verilog编写的lms算法。可实现自适应滤波功能-Lms algorithm written in verilog. Adaptive filtering can be achieved
Date : 2026-01-01 Size : 2kb User : he
[VHDL-FPGA-Verilog] adaptive_lms_equalizer_latest.tar DL : 0: It is the code for Adaptive Equalizer LMS Algorithm-It is the code for Adaptive Equalizer LMS Algorithm..!!
Date : 2026-01-01 Size : 25kb User : Adarsh
[VHDL-FPGA-Verilog] fir_lms DL : 0: 基于FIR滤波器的LMS自适应算法的FPGA实现-FIR filter based on LMS adaptive algorithm on FPGA
Date : 2026-01-01 Size : 5kb User : 庄辉
[VHDL-FPGA-Verilog] E7_3 DL : 0: 对基于符号LMS算法的自适应均衡器进行仿真。要求分别进行算法的性能仿真、生成FPGA测试用的输入信号、仿真权值在运算过程中的数据范围(The adaptive equalizer based on the symbol LMS algorithm is simulated. The performance simulation of the algorithm is required, the input signal for FPGA test is generated, and the data range of simulation weight in the operation process is required.)
Date : 2026-01-01 Size : 928kb User : SEXYLADY

« 12 »