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[VHDL-FPGA-Verilog] 原代码 DL : 0: 8051核的vhdl原代码。-8051 core VHDL source code.
Date : 2025-12-23 Size : 95kb User : 艾霞
[VHDL-FPGA-Verilog] pingpangchengxu DL : 0: 基于vhdl的实验仿真源码，包含完整的各项文件，是一个乒乓球游戏的小实验。-Linux embedded system based on the simulation source code, including the integrity of the document is a table tennis game is a small experiment.
Date : 2025-12-23 Size : 1.53mb User : 莫新康
[VHDL-FPGA-Verilog] linux DL : 0: 在硬件电路的设计中，会产生大量的Verilog HDL代码，由于这些代码是自动生成的，其文件名没有实际意义，代码没有注释，也没有相关的说明文档，给阅读和理解带来了不便-In the hardware circuit design, will produce a large number of Verilog HDL code, the code is automatically generated, the file name of no practical significance, code no comments, no relevant documentation, to read and understand the inconvenience
Date : 2025-12-23 Size : 45kb User : 朱鹏
[VHDL-FPGA-Verilog] r7lite DL : 0: R7Lite是基于Xilinx的Kintex7系列FPGA的PCI Express参考设计代码，PCIe 2.0 4x模式，包括了FPGA实现，Linux下驱动和测试例程。-R7Lite is a PCIe Reference design based on Xilinx Kintex7 FPGA,including FPGA code ,Linux Driver and Testing App
Date : 2025-12-23 Size : 20.67mb User : yao
[VHDL-FPGA-Verilog] fir DL : 0: This a verilog code for FIR filter works good on linux and windows platform-This is a verilog code for FIR filter works good on linux and windows platform
Date : 2025-12-23 Size : 1kb User : prad
[VHDL-FPGA-Verilog] fifo DL : 0: 基于verilog HDL的fifo设计与测试，包含设计与测试代码，以及简单的makefile编写。整个平台是基于linux操作，仿真平台是基于SYNOPSYS的vcs工具。(Based on verilog HDL fifo design and testing, including the design and test code, and simple makefile.The platform is based on Linux operating, the simulation platform is based on the VCS of SYNOPSYS tools.)
Date : 2025-12-23 Size : 15kb User : yzzls