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[VHDL-FPGA-Verilog] 8255 DL : 0: 8255参考设计VHDL源代码-The sound code of 8255 reference design based on VHDL
Date : 2025-12-30 Size : 221kb User :
[VHDL-FPGA-Verilog] VHDL的基本数学运算库 DL : 0: VHDL的基本数学运算库,非常好用-VHDL basic arithmetic library, a very handy! !
Date : 2025-12-30 Size : 227kb User :
[VHDL-FPGA-Verilog] VHDL语言基本数学运算库 DL : 0: VHDL语言基本数学运算库-VHDL basic arithmetic library
Date : 2025-12-30 Size : 242kb User : 崔广辉
[VHDL-FPGA-Verilog] arbit DL : 0: verilog 代码. 经验证成功,可以作为标准单元库,为FPGA设计者使用.-Verilog code. Certified success, as a standard cell library for the use of FPGA designers.
Date : 2025-12-30 Size : 5kb User : 宋昆仑
[VHDL-FPGA-Verilog] bidir DL : 0: verilog 代码. 经验证成功,可以作为标准单元库,为FPGA设计者使用.-Verilog code. Certified success, as a standard cell library for the use of FPGA designers.
Date : 2025-12-30 Size : 4kb User : 宋昆仑
[VHDL-FPGA-Verilog] library DL : 0: 介绍VHDL中库的调用，使对库的调用有深入的了解-VHDL introduction of library calls, so call for the Treasury have a deeper understanding of
Date : 2025-12-30 Size : 3kb User : chenwen
[VHDL-FPGA-Verilog] motor_control DL : 0: LIBRARY IEEE USE IEEE.STD_LOGIC_1164.ALL USE IEEE.STD_LOGIC_ARITH.ALL USE IEEE.STD_LOGIC_UNSIGNED.ALL
Date : 2025-12-30 Size : 1kb User : yu
[VHDL-FPGA-Verilog] EP2C5 DL : 0: Altera提供的CycloneII的orCAD封装库-Altera provided CycloneII the OrCAD library package
Date : 2025-12-30 Size : 8kb User : tony.chen
[VHDL-FPGA-Verilog] all_packages_20080525.tar DL : 0: FMF VHDL Models All the FMF models are VHDL 93 and VITAL 2000 compliant and require the VITAL 2000 library for correct compilation. They are designed for timing backannotation by means of an SDF file. The intrinsic delays default to 1 ns. We have a tool to read internal delays from an external file (in XML) and add them to the simulation through a SDF file. The most recent version is written in perl and may be downloaded from the "FMF Tools" area. Timing files are provided for over 11,500 part numbers. Also in the tools area is the document type definition (dtd) for the timing files. FMF MAKES NO WARRANTIES ON THE PERFORMANCE OF ANY MODELS IN ITS DATA REPOSITORY. USERS ARE RESPONSIBLE FOR VERIFYING THE ACCURACY OF THE MODELS, SOFTWARE OR TOOLS PROVIDED (TEST SUITES, PACKAGES, TIMING, ETC.).
Date : 2025-12-30 Size : 20kb User : ledo
[VHDL-FPGA-Verilog] gh_vhdl_lib_v3_48 DL : 0: The GH VHDL Standard Parts Library is a collection of basic VHDL parts that may be included in larger designs. There is nothing wrong with modifying library parts so that they will meet the system requirements.
Date : 2025-12-30 Size : 1.34mb User : 刘
[VHDL-FPGA-Verilog] verilog_cordic_core_latest.tar DL : 0: hi this verilog code for library
Date : 2025-12-30 Size : 355kb User : praveen
[VHDL-FPGA-Verilog] ddrsdram_verilog DL : 0: 内附doc是DDR SDRAM 参考设计文档；model包含SDRAM Verilog的模型；simulation包含verilog测试平台、modelsim工程文、设计库函数；source包含verilog源文件；synthesis包含工程的综合文件。-Enclosing the doc is a DDR SDRAM reference design documentation model contains SDRAM Verilog model simulation with verilog test platform, modelsim project text, design library function source contains the verilog source files synthesis comprehensive document that contains the project.
Date : 2025-12-30 Size : 734kb User : 陈少华
[VHDL-FPGA-Verilog] spartan3_hdl DL : 0: Xilinx Spartan3 library reference.
Date : 2025-12-30 Size : 2.48mb User : Chris
[VHDL-FPGA-Verilog] spartan3a_hdl DL : 0: Xilinx Spartan3E library reference.
Date : 2025-12-30 Size : 1.41mb User : Chris
[VHDL-FPGA-Verilog] Microchip_310806L DL : 0: Library Sample for Protel DXP - Maxim
Date : 2025-12-30 Size : 5.12mb User : Jan
[VHDL-FPGA-Verilog] C28xSoftwareTestBench(STB)Library DL : 0: This library contains the support modules for Software Test Bench (STB) framework.
Date : 2025-12-30 Size : 118kb User : zhouqijin
[VHDL-FPGA-Verilog] DXPintegrated-library DL : 0: dxp 集成库本指南知道如何在DXP中使用，创建和修改集成库。集成库将原理图及与他们相联系的PCB封装和（或）SPICE模型或信号完整性分析模型全部编译到一个不可编译的包中。所有的模型信息都从模型库或文件拷贝到集成库里，所以无论原始源库在什么地方，所有的元件信息被存储在一起。这样做集成库真正可以随意移动。 -dxp integrated library DXP this guide to know how to use, create and modify an integrated library. Schematic diagram of an integrated library will be associated with their PCB assembly and (or) SPICE models or signal integrity models all compiled into a non-compiled package. All the model information from the model files to the integration of library or library, so no matter where the original source and sink, all the component information is stored together. This integrated library really can move.
Date : 2025-12-30 Size : 1.36mb User : shl
[VHDL-FPGA-Verilog] add-simulation-library DL : 0: 在ModelSimSE中添加ALTERA仿真库的详细步骤，自己试过，可用！-detail steps to add ModelSimSE ALTERA simulation library, I tried, available!
Date : 2025-12-30 Size : 209kb User : yeqy
[VHDL-FPGA-Verilog] Embedded-JPEG-Codec-Library DL : 0: An open source JPEG codec library optimized for embedded system, including both encoder and decoder. Compact, optimized for specific hardware, easy to be ported to various embedded OS, ESL tools like Handel-C, multi-processor systems and FPGA.
Date : 2025-12-30 Size : 160kb User : will
[VHDL-FPGA-Verilog] dtysky-FPGA-Imaging-Library-c8cd350 DL : 0: 一个hls视频库ip libraries，里面包含各种功能的ip核，可进行复用。-A hls video library ip libraries, which contains a variety of functions of the ip core can be reused.
Date : 2025-12-30 Size : 1.31mb User : 黄蔚

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