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[VHDL-FPGA-Verilog] jop_core_cache DL : 0: JOP的内核缓存源码，不易找到，大家一定要顶啊-JOP kernel source code cache, not easy to find, we must kits
Date : 2026-01-10 Size : 1kb User : 黄肖超
[VHDL-FPGA-Verilog] jop_core_core DL : 0: JOP的内核文件，这是核心的核心，中文资料基本找不到-JOP kernel, which is the core of the core, the Chinese can not find basic information
Date : 2026-01-10 Size : 2kb User : 黄肖超
[VHDL-FPGA-Verilog] SPI_VHDL DL : 0: SPI串口的内核实现（vhdl）,可以用qII等软件直接加到FPGA或者CPLD里面.-the SPI Serial Kernel (vhdl) can be used directly qII software foisted CPLD or FPGA inside.
Date : 2026-01-10 Size : 13kb User : efly
[VHDL-FPGA-Verilog] 8051core_vhdl DL : 0: 8051的内核(vhdl) This is version 1.1. of the MC8051 IP core. 在FPGA上运行.供有精力的人研究.-8051 kernel (vhdl) This is version 1.1. Of the M C8051 IP core. FPGA operation. have the energy for the study.
Date : 2026-01-10 Size : 208kb User : efly
[VHDL-FPGA-Verilog] mc8051design DL : 0: VHDL写的8051内核,可用的,好用,有兴趣可下载,在外国网站下载的-write VHDL 8051 kernel, available, convenient, can be downloaded interested in the foreign website
Date : 2026-01-10 Size : 399kb User : lbh
[VHDL-FPGA-Verilog] cpld(huaqi) DL : 0: 上海外滩看到的最大的LED显示屏的内核源代码，主要是完成视频信号的远距离传输的编解码与接口转换-Shanghai Bund to see the largest LED display in the kernel source code, mainly to complete the long-distance video signal transmission codec conversion and interface
Date : 2026-01-10 Size : 473kb User : liao
[VHDL-FPGA-Verilog] JTD DL : 0: 在maxplusII平台上开发的一个交通等内核，该文件中有多个版本，为实现交通灯的不同功能，同时后续版本也是对前面版本的修改与优化，基于verilog HDL语言-MaxplusII platform in the development of a transport kernel, the document has multiple versions, in order to realize the different functions of traffic lights, at the same time is also a follow-up version of the previous version of the modification and optimization, based on verilog HDL language
Date : 2026-01-10 Size : 1.13mb User : 孙炜
[VHDL-FPGA-Verilog] SPI_verilog_vhdl DL : 0: SPI串口的内核实现分verilog和HDLC实现-SPI serial kernel realize realize sub-Verilog and HDLC
Date : 2026-01-10 Size : 13kb User : qian
[VHDL-FPGA-Verilog] FPGA DL : 0: FPGA设计全流程：Modelsim>>Synplify.Pro>>ISE 第一章 Modelsim编译Xilinx库第二章调用Xilinx CORE-Generator 第三章使用Synplify.Pro综合HDL和内核第四章综合后的项目执行第五章不同类型结构的仿真-FPGA design of the whole process: Modelsim>> Synplify.Pro>> ISE Chapter ModelSim Xilinx compiler library chapter called Xilinx CORE-Generator Chapter III Synplify.Pro integrated use of Chapter IV of HDL and kernel integrated implementation of the project after the Chapter V structure of different types of simulation
Date : 2026-01-10 Size : 213kb User : 青岚之风
[VHDL-FPGA-Verilog] 8051Core DL : 0: 8051IP内核的源码，内有vhdl源代码，希望对大家有帮助-8051IP kernel source code, with VHDL source code, I hope all of you help
Date : 2026-01-10 Size : 1.09mb User : sylivian
[VHDL-FPGA-Verilog] 8051core-Verilog DL : 1: 8051core-Verilog FPGA的51单片机内核源代码! -8051core-Verilog FPGA 51 Singlechip kernel source code!
Date : 2026-01-10 Size : 51kb User : EYE
[VHDL-FPGA-Verilog] mc8051 DL : 0: mc8051内核,VHDL程序,内有说明,超详细.-mc8051 kernel, VHDL program, which has made it clear, super-detailed.
Date : 2026-01-10 Size : 197kb User : dushibiao
[VHDL-FPGA-Verilog] TUT1_BASIC1_7C5TP DL : 0: FPGA中嵌入8052内核，功能和直接使用52完全相同，但频率可以达到200M.-8052 embedded FPGA kernel, function and use directly exactly the same, but the frequency of 52 blast-caused can achieve.
Date : 2026-01-10 Size : 4.75mb User : shengxi
[VHDL-FPGA-Verilog] Test_Plg_18 DL : 0: 基于FPGA的等精度频率测试仪,测量范围1HZ到100M.已调试成功.采用康芯公司的FPGA开发板,嵌入51内核程序.-FPGA-based test instrument such as the frequency accuracy, measurement range 1HZ to 100M. Has been a successful debugging. Using Kang' s FPGA core development board, embedded in 51 kernel.
Date : 2026-01-10 Size : 5.03mb User : 李恺君
[VHDL-FPGA-Verilog] NIOS_II_SOPC_Develop DL : 0: 介绍如何利用 NIOS II 內核，来做嵌入式SOPC開發-How to implement an Embedd SOPC development by using NIOS II kernel.
Date : 2026-01-10 Size : 86kb User : 邓文凯
[VHDL-FPGA-Verilog] socdesignandtest DL : 0: SoC是系统级集成，将构成一个系统的软/硬件集成在一个单一的IC芯片里，它一般包含片上总线、MPU核、SDRAM/DRAM、FLASH ROM、DSP、A/D、D/A、RTOS内核、网络协议栈、嵌入式实时应用程序等模块，同时，它也具有外部接口，如外部总线接口和I/O端口。通常，SoC中包含的一些模块是经过预先设计的系统宏单元部件（Macrocell）或核（Cores），或者例程（Routines），称为IP模块，这些模块都是可配置的，因此，基于SoC的设计方法学也称为基于IP的嵌入式系统设计方法学。 -SoC is a system-level integration, will constitute a system of hardware/software integrated in a single IC chip inside, which generally includes on-chip bus, MPU core, SDRAM/DRAM, FLASH ROM, DSP, A/D, D/A, RTOS kernel, network protocol stack, embedded real-time applications and other modules, the same time, it also has an external interface, such as external bus interface and I/O ports. Usually, SoC modules are included some of the pre-designed system macro-cell components (Macrocell) or nuclear (Cores), or routine (Routines), known as IP modules that are configurable, so, based on the SoC The design methodology is also known as IP-based embedded system design methodology.
Date : 2026-01-10 Size : 312kb User : yyj
[VHDL-FPGA-Verilog] EMV96 DL : 0: This emv96 kernel code. It is useful for point of sale programmers.-This is emv96 kernel code. It is useful for point of sale programmers.
Date : 2026-01-10 Size : 531kb User : deneme
[VHDL-FPGA-Verilog] FPGA_OS DL : 0: 一个FPGA芯片上搭建系统的实例，包含了内核的建立，及在内核上运行的简单程序。-FPGA chip to build a system example, contains a kernel build, and run in the kernel of simple procedures.
Date : 2026-01-10 Size : 8.46mb User : 杨军
[VHDL-FPGA-Verilog] CVI-SCOPE DL : 0: 用开发板内核来实现FPGA开发板通过USB端口通信程序-Development board with FPGA development board to implement the kernel through the USB port communication program
Date : 2026-01-10 Size : 375kb User : jiang
[VHDL-FPGA-Verilog] modelsim6.0 DL : 0: Mentor公司的ModelSim是业界最优秀的HDL语言仿真软件，它能提供友好的仿真环境，是业界唯一的单内核支持VHDL和Verilog混合仿真的仿真器。-Mentor' s ModelSim is the industry' s best HDL language simulation software, it can provide a friendly simulation environment, the industry' s only single-kernel support for mixed VHDL and Verilog simulation of the simulator.
Date : 2026-01-10 Size : 379kb User : 王阳

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