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[VHDL-FPGA-Verilog] sssss DL : 0: 掌握FPGA可编程门阵列的基本方法 2)．掌握Xilinx ISE 9.0的基本使用方法以及在ise的环境下导入51核及其配置方法 3)．学会将keil编译成功个hex文件变为coe文件，导入例化的rom 4)．学习设计核的关键与方法 -Programmable Gate Array FPGA to master the basic method 2). Xilinx ISE 9.0 to grasp the basic use and the environment in the ise 51 nuclear import and configuration 3). Keil compiler will successfully learn a hex file into coe file, import the cases of the rom 4). The key learning design and methods of nuclear
Date : 2026-01-12 Size : 390kb User : liujia
[VHDL-FPGA-Verilog] MC8051 DL : 0: FPGA的8051 IP核，完整的工程，直接用Keil编写好单片机代码后将生成的HEX文件放进FPGA的ROM里面，便可使用，比51单片机速度更快！-FPGA-8051 IP core, the complete works directly with Keil to write a good microcontroller code will be generated HEX file into the FPGA-ROM which can be used faster than the speed of 51 single-chip
Date : 2026-01-12 Size : 2.86mb User : laiqingsong
[VHDL-FPGA-Verilog] C51 DL : 0: 基于5-1单片机环境噪声测量仪的设计，包含主程序、中断服务程序、显示程序、(Based on 51 single-chip environmental noise detector proteus simulation file containing a set of project files noise.dsn Keil main code main.c 6 relevant articles and graduation thesis design through simulation)
Date : 2026-01-12 Size : 2kb User : 哈哈哈哈3