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[VHDL-FPGA-Verilog] jtag0 DL : 0: 本程序使用vhdl编写的jtag接口实现程序,其中有些功能未能实现,希望有人能够帮忙完善!-vhdl the procedures used to prepare the jtag interface procedures, which some of them did not materialize, hope someone can help perfect!
Date : 2026-01-11 Size : 84kb User : 马斌
[VHDL-FPGA-Verilog] jtag.tar DL : 0: Date : 2026-01-11 Size : 331kb User : dc
[VHDL-FPGA-Verilog] jtag DL : 0: jtag技术规范，以及标准的并口jtag下载电缆的资料-JTAG technical specifications, as well as the standard parallel port JTAG download cable data
Date : 2026-01-11 Size : 12kb User : 张恒
[VHDL-FPGA-Verilog] core_arm.tar DL : 0: ARM7系统IP核的VHDL语言源代码，需要的开发环境是QUARTUS II 6.0。-ARM7 System IP Core VHDL language source code, the need for the development environment is QUARTUS II 6.0.
Date : 2026-01-11 Size : 651kb User : 周华茂
[VHDL-FPGA-Verilog] msp430_jtag_nios DL : 0: 将msp430与使用nios的fpga相连，将fpga作为msp430的jtag使用。其中用到了nios内的多种接口以及dma操作-The MSP430 with the use of the Nios FPGA connected to the FPGA as the MSP430 JTAG to use. Which used the Nios multiple interfaces and dma operation
Date : 2026-01-11 Size : 55kb User : danielmu
[VHDL-FPGA-Verilog] jtag_logic DL : 0: 这是自制altera usb_blaster所用到的CPLD程序，用VHDL语言写的。
Date : 2026-01-11 Size : 2kb User : wdy2004
[VHDL-FPGA-Verilog] USB_jtag DL : 0: 用verilog编写的USB下载线程序实现USB协议和JTAG接口的数据转换实现状态机。-Verilog prepared using USB download cable program realize USB protocol and JTAG interface to achieve data conversion state machine.
Date : 2026-01-11 Size : 1.5mb User : 霍飘摇
[VHDL-FPGA-Verilog] EPM7128SLC84-10chengxushili DL : 0: CPLD程序，ALTERA公司的EPM7128SLC84-10,PLCC84封装，已经调试过的程序，包含仿真文件，波形文件，VHDL语言程序，电路图以及PCB板和系统原理图，非常有用，尤其是初学EDA和CPLD、FPGA器件的人-CPLD procedures, ALTERA Corporation EPM7128SLC84-10, PLCC84 package, has been testing the procedure, including the simulation files, wave files, VHDL language program, circuit boards and systems, as well as PCB schematics, very useful, especially the beginner EDA and the CPLD, FPGA devices were
Date : 2026-01-11 Size : 152kb User : xiaobo
[VHDL-FPGA-Verilog] 45561564 DL : 0: 典型实例10.8 字符LCD接口的设计与实现软件开发环境：ISE 7.1i 硬件开发环境：红色飓风II代－Xilinx版 1. 本实例控制开发板上面的LCD的显示； 2. 工程在\project文件夹里面 3. 源文件和管脚分配在\rtl文件夹里面 4. 下载文件在\download文件夹里面,.mcs为PROM模式下载文件,.bit为JTAG调试下载文件。-Typical examples of character LCD interface 10.8 The Design and Implementation of Software Development Environment: ISE 7.1i development environment hardware: Hurricane II on behalf of the red-Xilinx Edition 1. The above examples of the control board of the LCD display 2. Projects \ project folder inside 3. the distribution of the source file and pin in \ rtl folder inside 4. download files in \ download folder inside,. mcs file for the PROM mode download,. bit for the JTAG debugger to download the file.
Date : 2026-01-11 Size : 306kb User : 王磊
[VHDL-FPGA-Verilog] JTAG DL : 0: actel FPGA JTAG电路周立功开发-actel JTAG
Date : 2026-01-11 Size : 32kb User : pigeoon
[VHDL-FPGA-Verilog] Exp6-VGA DL : 0: Create-SOPC1000X 嵌入式开发平台、用于 FGPA的 JTAG 下载电缆、VGA显示器、串口数据线、PC主机。 -Create-SOPC1000X embedded development platform for FGPA the JTAG download cable, VGA display, serial data cable, PC host.
Date : 2026-01-11 Size : 647kb User : yangcheng
[VHDL-FPGA-Verilog] TechXclusives-ReconfiguringBlockRAMs DL : 0: Xilinx FPGA block RAM reconfig via JTAG
Date : 2026-01-11 Size : 102kb User : Kraja
[VHDL-FPGA-Verilog] JTAG DL : 0: JTAG Verilog source code
Date : 2026-01-11 Size : 13kb User : austin
[VHDL-FPGA-Verilog] jtag DL : 0: Fpga开发应用，jtag方面的源代码，VHDL-Fpga development and application, jtag in the source code, VHDL
Date : 2026-01-11 Size : 3kb User : 王刚
[VHDL-FPGA-Verilog] IPcore DL : 0: 非常有用的IP核资源，里面包含了JTAG,MEMORY,PCI，SDRAM和USB1.1等内容，期望对大家有用-A very useful IP core resources, which includes the JTAG, MEMORY, PCI, SDRAM, and USB1.1 and other content, expectations for all of us
Date : 2026-01-11 Size : 882kb User : 李同滨
[VHDL-FPGA-Verilog] uart DL : 0: 程序说明: 本次实验控制开发板上面的串口，与PC机进行通信，并在串口精灵里面显示字符。目录说明: 工程在\project文件夹里面源文件和管脚分配在\rtl文件夹里面下载文件在\download文件夹里面,.mcs为PROM模式下载文件,.bit为JTAG调试下载文件。-Procedure Note: The experimental control development board above the serial port to communicate with the PC machine, and the serial wizard inside the display characters. Catalog Description: The project \ project folder inside the source file and pins distributed in \ rtl folder inside download the file in the \ download folder inside,. Mcs for the PROM mode download files,. Bit for the JTAG debug download the file.
Date : 2026-01-11 Size : 884kb User : 军军
[VHDL-FPGA-Verilog] usb DL : 0: 程序说明: 本次实验控制开发板USB，与PC机进行通信，并在显示字符。目录说明: 工程在\project文件夹里面源文件和管脚分配在\rtl文件夹里面下载文件在\download文件夹里面,.mcs为PROM模式下载文件,.bit为JTAG调试下载文件。-Procedure Note: In this experiment, control development board USB, and PC, to communicate, and display character. Catalog Description: The project \ project folder inside the source file and pins distributed in \ rtl folder inside download the file in the \ download folder inside,. Mcs for the PROM mode download files,. Bit for the JTAG debug download the file.
Date : 2026-01-11 Size : 79kb User : 军军
[VHDL-FPGA-Verilog] jtag DL : 1: verilog jtag源码及原理，还有debug模块。边界扫描等-verilog jtag source and principle, as well as debug module. Boundary-Scan, etc.
Date : 2026-01-11 Size : 9.58mb User : jack
[VHDL-FPGA-Verilog] usb_jtag DL : 0: usb通过Jtag口进行下载的源码程序，可以方便的通过它下载到EPROM里面-usb port for downloading through the Jtag source programs can be easily downloaded to the EPROM which through its
Date : 2026-01-11 Size : 97kb User : 邓旺波
[VHDL-FPGA-Verilog] Using-JTAG-PROMs-for-data-storage DL : 0: Xilinx FPGA的配置中，从Flash中读写用户数据，包括VHDL、Verilog程序-in configuring Xilinx FPGA,reading and writing user data from flash,including the VHDL and Verilog code
Date : 2026-01-11 Size : 155kb User : 赵齐

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