Search - iteration

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[VHDL-FPGA-Verilog] diedai DL : 0: 通过设置矩阵大小数，自动地利用雅克比迭代和高斯赛德尔迭代计算结果以及利用范数计算误差-Matrix size by setting the number of auto-use and high Sisaideer Jacobi iteration iterative calculations and the use of norm calculation errors
Date : 2026-01-01 Size : 12kb User : 李亚丽
[VHDL-FPGA-Verilog] cordic_new DL : 0: Cordic with very high resolution. This program is developped by me. the maximal error is 0.04. You can use it for angle calculation.-Cordic with very high resolution. This program is developped by me. the maximal error is 0.04. You can use it for angle calculation. This original program can be seen in the book: digital processing with FPGA (Uwe Baese), the disadvantage is that the logic cells increases with iteration steps. You can also try this program using state machine instead of this pipeline.
Date : 2026-01-01 Size : 1kb User : 包一明
[VHDL-FPGA-Verilog] cordic DL : 0: we propose a low-cost sequential and high performance architecture for the implementation of CORDIC algorithm in two computation modes. It suited for serial operation that performs conversion between polar and rectangular coordinate systems, essentially sin/cos, sinh/cosh and arctan computation. In our proposed architecture, radix-2 arithmetic is employed. The design targets real time application of fingerprint recognition. We present our VHDL description of CORDIC algorithm. To reduce iteration delay, we used some combinatory blocks. Fixed point arithmetic was considered. To valid our conception and its CORDIC accuracy, we present relative error calculated in convergence range for some trigonometric and hyperbolic functions. Our architecture was implemented and tested. The contribution of the paper includes the CORDIC design flow. -we propose a low-cost sequential and high performance architecture for the implementation of CORDIC algorithm in two computation modes. It suited for serial operation that performs conversion between polar and rectangular coordinate systems, essentially sin/cos, sinh/cosh and arctan computation. In our proposed architecture, radix-2 arithmetic is employed. The design targets real time application of fingerprint recognition. We present our VHDL description of CORDIC algorithm. To reduce iteration delay, we used some combinatory blocks. Fixed point arithmetic was considered. To valid our conception and its CORDIC accuracy, we present relative error calculated in convergence range for some trigonometric and hyperbolic functions. Our architecture was implemented and tested. The contribution of the paper includes the CORDIC design flow.
Date : 2026-01-01 Size : 2kb User : Nihel Neji
[VHDL-FPGA-Verilog] modelsim-run-one-step--Error- DL : 0: 用modesim仿真的时候会出现只运行了一步就不动了，显示"# ** Error: (vsim-3601) Iteration limit reached at time 0 ps."的解决方法。-With modesim simulation run only when there will be a step not move, display " #** Error: (vsim-3601) Iteration limit reached at time 0 ps." Solution.
Date : 2026-01-01 Size : 6kb User : dengyaohui
[VHDL-FPGA-Verilog] Circular-CORDIC-in-Vectoring-Mode DL : 0: The first iteration rotates the vectors the second or third quadrant to the first or fourth, respectively. The shift sequence is 0,0,1, and 2. The rotation angle of the first four steps becomes: arctan(∞) = 90◦ , arctan(20) = 45◦ , arctan(2− 1) = 26.5◦ , and arctan(2− 2) = 14◦ . -The first iteration rotates the vectors the second or third quadrant to the first or fourth, respectively. The shift sequence is 0,0,1, and 2. The rotation angle of the first four steps becomes: arctan(∞) = 90◦ , arctan(20) = 45◦ , arctan(2− 1) = 26.5◦ , and arctan(2− 2) = 14◦ .
Date : 2026-01-01 Size : 274kb User : hooman hematkhah
[VHDL-FPGA-Verilog] sxcxb DL : 0: Jacobi iteration for solving linear equations class-based, Pattern Recognition bayes discriminant analysis algorithm, The commonly used digital signal modulation based on artificial neural network.
Date : 2026-01-01 Size : 8kb User : koujenlangfao
[VHDL-FPGA-Verilog] pen_cv14 DL : 0: Thermonuclear using weighting factors Jacobi iteration for solving linear equations class-based, Is a two hidden layer back propagation neural network.
Date : 2026-01-01 Size : 5kb User : sengqingsanpao
[VHDL-FPGA-Verilog] icivd DL : 0: Acquisition and Processing of the speech signal, digital signal processing class-based, Various resource allocation algorithm, Jacobi iteration for solving linear equations class-based.
Date : 2026-01-01 Size : 9kb User : faogiumaobun