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[VHDL-FPGA-Verilog] float_mul_verilog DL : 1: 浮点乘法verilog代码，浮点格式遵循 IEEE754 标准。-Float Point Multiply , im verilog
Date : 2025-12-24 Size : 2kb User : gongwen
[VHDL-FPGA-Verilog] bcd2bin_n DL : 0: This decoder binary to Binary Coded Decimal. Im tested on s3e-This is decoder binary to Binary Coded Decimal. Im tested on s3e
Date : 2025-12-24 Size : 1kb User : luk
[VHDL-FPGA-Verilog] PIPE_LINING_CPU_TEAM_24 DL : 0: 采用Quatus II编译环境，使用Verilog HDL语言编写实现了五段流水线CPU。能够完成以下二十二条指令（均不考虑虚拟地址和Cache，并且默认为小端方式）： add rd,rs,rt addu rd,rs,rt addi rt,rs,imm addiu rt,rs,imm sub rd,rs,rt subu rd,rs,rt nor rd,rs,rt xori rt,rs,imm clo rd,rs clz rd,rs slt rd,rs,rt sltu rd,rs,rt slti rt,rs,imm sltiu rt,rs,imm sllv rd,rt,rs sra rd,rt,shamt blez rs,imm j target lwl rt,offset(base) lwl rt,offset(base) lw rt,imm(rs) sw rt,imm(rs) 在本设计中，采取非常良好的模块化编程风格，共分十三个主要模块PIPE_LINING_CPU_TEAM_24.v为顶层实体文件，对应为PIPE_LINING_CPU_TEAM_24模块作为顶层实体模块，如下： ifetch.v、regdec.v、exec.v、mem.v、wr.v分别实现五个流水段； cpuctr.v用于产生CPU控制信号； ALU.v用于对操作数进行相应指令的运算并输出结果； DM.v数据存储器 IM.v指令存储器 datareg.v数据寄存器堆 extender.v位扩展 yiwei_32bits.v 实现32位四种移位方式的移位器在顶层实体中，调用ifetch.v、regdec.v、exec.v、mem.v、wr.v这五个模块就实现了流水线CPU。顶层模块的结构清晰明了。对于学习verilog编程非常有用- Quatus II compiled by the environment, using Verilog HDL language to achieve a five-stage pipeline CPU. To complete the following 22 commands (not considering the virtual address and Cache, and the default mode for the small end): add rd, rs, rt addu rd, rs, rt addi rt, rs, imm addiu rt, rs, imm sub rd, rs, rt subu rd, rs, rt nor rd, rs, rt xori rt, rs, imm clo rd, rs clz rd, rs slt rd, rs, rt sltu rd, rs, rt slti rt, rs, imm sltiu rt, rs, imm sllv rd, rt, rs sra rd, rt, shamt blez rs, imm j target lwl rt, offset (base) lwl rt, offset (base) lw rt, imm (rs) sw rt, imm (rs) In this design, take a very good modular programming style, is divided into 13 main modules PIPE_LINING_CPU_TEAM_24.v for the top-level entity file, the corresponding module as a top-level entity for the PIPE_LINING_CPU_TEAM_24 modules, as follows: ifetch.v, regdec.v, exec.v, mem.v, wr.v water were to achieve the five paragraph cpuctr.v used to generate CPU control signal ALU.v accordingly
Date : 2025-12-24 Size : 4.72mb User : 石
[VHDL-FPGA-Verilog] Hamming_decoder-1 DL : 0: this program does something im not sure what but all i want is to get into the damn site thank you
Date : 2025-12-24 Size : 200kb User : therock5591
[VHDL-FPGA-Verilog] AN123 DL : 0: AMBA Application Note: AN123 - Logic Tile IT1 GPIO example design. -Application note AN123 provides all of the AHB slave features of AN119 with the addition of five 32bit AHB GPIO slaves. The GPIO interfaces are used to configure and test an IT1 board. The following board combinations are supported: Core Module+ Integrator/IM-LT1+ LT-XC2V6000+ IT1 Core Module+ Integrator/IM-LT1+ LT-XC2V8000+ IT1 Integrator/CP+ Core Module+ Integrator/IM-LT1+ LT-XC2V6000+ IT1 Integrator/CP+ Core Module+ Integrator/IM-LT1+ LT-XC2V8000+ IT1 PB926EJ-S+ LT-XC2V6000+ IT1 PB926EJ-S+ LT-XC2V8000+ IT1 Asynchronous and Synchronous bridge modes are supported on the PB926EJ-S with different design images. Asynchronous mode is selected using SW1[3] on the PB926EJ-S.
Date : 2025-12-24 Size : 4.27mb User : 余曉民
[VHDL-FPGA-Verilog] AN136 DL : 0: AMBA Application Note: AN136 - Using Core Tiles stand-alone. -AMBA Application Note: AN136- Using Core Tiles stand-alone. This example design shows how to use Core Tiles as individual units powered through an IM-LT1. A Logic Tile is also required. The following board combinations are supported: Integrator/IM-LT1+ {LT-XC2V6000+ CTxxx}+ ... Integrator/IM-LT1+ {LT-XC2V8000+ CTxxx}+ ... Integrator/IM-LT1+ {LT-XC2V6000+ CT926EJ-S}+ {IT1}+ ... Integrator/IM-LT1+ {LT-XC2V8000+ CT926EJ-S}+ {IT1}+ ...
Date : 2025-12-24 Size : 5.2mb User : 余曉民
[VHDL-FPGA-Verilog] AN128 DL : 0: AMBA Application Note: AN128 - Logic Tile Flashing LED design. -AMBA Application Note: AN128- Logic Tile Flashing LED design. Application note AN128 is a simple flashing LED example design to demonstrate the process of creating FPGA images and programming them into Logic Tiles. The following board combinations are supported: Logic Tiles LT-XC2V6000 LT-XC2V8000 LT-XC4VLX160 LT-XC4VLX200 LT-XC5VLX330 running on top of baseboards IM-LT1 EB+ CT7TDMI EB+ CT926EJ-S EB+ CT1136JF-S EB+ CT1156T2F-S EB+ CT1176JZF-S EB+ CT11MPCore PB1176JZF-S PB11MPCore PBA8
Date : 2025-12-24 Size : 35.05mb User : 余曉民
[VHDL-FPGA-Verilog] UART DL : 0: IM DESINING VHDL COD EIN IS THIS CODE IS GOD AND TESTIN VERY GOOD
Date : 2025-12-24 Size : 964kb User : mehdi
[VHDL-FPGA-Verilog] fp-im-of DL : 0: its abt in vhdl ,frequency estiator
Date : 2025-12-24 Size : 7kb User : bhagyalaxmi