Search - ie - CodeBus

Search - ie - List

[VHDL-FPGA-Verilog] SELLER DL : 0: 基于verilog HDL的自动售货机控制电路设计: 可以对5种不同种类的货物进行自动售货,价格分别为A=1.00,B=1.50,C=1.80,D=3.10,E=5.00 。售货机可以接受1元,5角,1角三种硬币(即有三种输入信号IY,IWJ,IYJ),并且在一个3位7段LED(二位代表元,一位代表角)显示以投入的总钱数，最大9.90元，如果大于该数值，新投入的硬币会退出,选择货物的输入信号Ia,Ib,Ic,Id,Ie和一个放弃信号In,输出指示信号为 Sa, Sb ,Sc ,Sd, Se 分别表示售出相应的货物,同时输出的信号yuan, jiao代表找零,相应每个脉冲代表找零相应的硬币，上述输入和输出信号均是一个固定宽度的脉冲信号。
Date : 2026-01-10 Size : 1kb User : chenyi
[VHDL-FPGA-Verilog] oc_i2c_masterI2CIP DL : 0: *** ***OC_I2C_Master使用说明*** ***** 使用步骤：1.将OC_I2C_Master文件夹拷贝到安装盘\altera\kits\nios2\components目录下。之后重新打开SOPC Builder，在可用元件列表的DeviceSOPC组中将出现OC_I2C_Master 元件，即可像其它Altera外设元件一样添加和使用。 2.hdl文件夹中包含有描述i2c逻辑的硬件描述文件，不能删除。 3.HAL文件夹包含硬件抽象层所需的文件（即驱动），不能删除。 4.inc文件夹包含有定义底层硬件的C语言头文件，不能删除. 5.I2C_doc文件夹下有关于该元件的开发文档。-********* OC_I2C_Master use*********** use these steps: 1. OC_I2C_Master folder will be copied to the installation disk alterakits ios2components directory. Re-open after the SOPC Builder, a list of available devices will appear DeviceSOPC Group OC_I2C_Master components, can be similar to other peripheral devices like Altera add and use. 2.hdl folder contains logical description i2c hardware description files, can not be deleted. 3.HAL folder contains the necessary hardware abstraction layer file (ie drivers), can not be deleted. 4.inc folder contains the definition of the underlying hardware C language header files, should not delete. 5.I2C_doc folder on the development of document components.
Date : 2026-01-10 Size : 188kb User : 姓名
[VHDL-FPGA-Verilog] VHDL DL : 0: VHDL ieee标准及书籍-VHDL ieee standards and books
Date : 2026-01-10 Size : 1.45mb User : haiwaw
[VHDL-FPGA-Verilog] pll DL : 0: DPLL由鉴相器、模K加减计数器、脉冲加减电路、同步建立侦察电路、模N分频器构成. 整个系统的中心频率(即signal_in和signal_out的码速率的2倍)为clk/8/N. 模K加减计数器的K值决定DPLL的精度和同步建立时间,K越大,则同步建立时间长,同步精度高.反之则短,低. -DPLL by the phase detector, K addition and subtraction counter mode, pulse subtraction circuit, synchronous detection circuit established, constitute a model N divider. The whole system of the center frequency (ie signal_in and signal_out the code rate of 2 times) to clk/8/N. modulus K K value addition and subtraction counter DPLL decision to establish the accuracy and synchronization time, K is larger, the simultaneous establishment of a long time, synchronization accuracy. contrary is short and low.
Date : 2026-01-10 Size : 1kb User : 鬼舞十七
[VHDL-FPGA-Verilog] XC4VLX60MB_Lab5_PROM_ISE91 DL : 0: XCVLXMB the board Xilinx SRAM_BASED FPGA design is the main element Pieces, SRAM_BASED the FPGA, the design began to verify the results, may experience many changes, this time as long as the JTAG s DOWNLOAD CABLE with the IMPACT software is continuously recordable BIT file to the FPGA, you can verify the results, such as Lab1 ~ Lab4 are conducted in this manner, the design. But in the end, if required to maintain the final version of the file, you need to first convert through BIT MCS file, then burn the file records to the PROM MCS inside, after the burn is complete, FPGA can set the M0, M1, M2 s pick Pin 000 (ie Mater Slave Mode), so off power after the next boot, FPGA from the PROM auto-complete Confogurtion, In order to keep this file can be permanent.-XCVLXMB the board Xilinx SRAM_BASED FPGA design is the main element Pieces, SRAM_BASED the FPGA, the design began to verify the results, may experience many changes, this time as long as the JTAG' s DOWNLOAD CABLE with the IMPACT software is continuously recordable BIT file to the FPGA, you can verify the results, such as Lab1 ~ Lab4 are conducted in this manner, the design. But in the end, if required to maintain the final version of the file, you need to first convert through BIT MCS file, then burn the file records to the PROM MCS inside, after the burn is complete, FPGA can set the M0, M1, M2' s pick Pin 000 (ie Mater Slave Mode), so off power after the next boot, FPGA from the PROM auto-complete Confogurtion , In order to keep this file can be permanent.
Date : 2026-01-10 Size : 776kb User : vkiy
[VHDL-FPGA-Verilog] zidongpinlv DL : 0: 4位自动换挡数字频率计设计 1、由一个4位十进制数码管（含小数点）显示结果； 2、测量范围为1Hz~9999KHz； 3、能自动根据7位十进制的结果，自动选择有效数据的高4位进行动态显示（即量程自动转换），小数点表示是千位，即KHz； 4、为检测设计正确与否，应将时钟通过PLL和手控分频器产生宽范围的多个频率来测试自动换档频率计功能。 -4 automatic transmission design a digital frequency meter, by a 4 decimal digital tube (including the decimal point) shows the results 2, the measuring range 1Hz ~ 9999KHz 3, can automatically according to seven decimal results, automatically select valid data dynamic display of high 4 (ie, automatic range conversion), the decimal point that is 1000, which KHz 4, for the detection of design right or not, should be through the PLL and clock dividers generate wide range of manual multiple frequency Test automatic transmission frequency counter function.
Date : 2026-01-10 Size : 346kb User : 李伦特
[VHDL-FPGA-Verilog] serial DL : 0: 本模块的功能是验证实现和PC机进行基本的串口通信的功能。需要在PC机上安装一个串口调试工具来验证程序的功能。程序实现了一个收发一帧10个bit（即无奇偶校验位）的串口控制器，10个bit是1位起始位，8个数据位，1个结束位。串口的波特律由程序中定义的div_par参数决定，更改该参数可以实现相应的波特率。程序当前设定的div_par 的值是0x104，对应的波特率是9600。用一个8倍波特率的时钟将发送或接受每一位bit的周期时间划分为8个时隙以使通信同步. 程序的基本工作过程是，按动一个按键SW0，控制器向PC的串口发送“welcome"， PC机接收后显示验证数据是否正确（串口调试工具设成按ASCII码接受方式）. PC可随时向CPLD发送0-F的十六进制数据，CPLD接受后显示在7段数码管上.-The module s function is to verify the implementation and the basic PC, the serial communication function. Need PC, Install a serial debugging tools to verify the functionality of the program. Program implements a receive a 10 bit (ie no parity bit) of the serial controllers, 10 bit is a start bit, 8 data bits, 1 stop bit. Serial Porter law defined by the program parameters div_par decision can change the parameters of the corresponding Baud rate. Program the value of the current set div_par Is 0x104, the corresponding baud rate is 9600. 8 times the baud rate with a clock will be sent or received per A bit of the cycle time is divided into eight time slots in order to pass Information synchronization. The basic process is the work program, press a button SW0, the controller s serial port to the PC "Welcome", PC, after receiving the authentication data displayed is correct (serial debugging tool ASCII code set by the r
Date : 2026-01-10 Size : 2kb User : riversky
[VHDL-FPGA-Verilog] serial DL : 0: 本模块的功能是验证实现和PC机进行基本的串口通信的功能。需要在PC机上安装一个串口调试工具来验证程序的功能。程序实现了一个收发一帧10个bit（即无奇偶校验位）的串口控制器，10个bit是1位起始位，8个数据位，1个结束位。-The module' s function is to verify the implementation and the basic PC, the serial communication function. Installed on the PC requires a serial port debug tool to verify the functionality of the program. Program implements a receive a 10 bit (ie no parity bit) of the serial controller, 10 bit is a start bit, 8 data bits, 1 stop bit.
Date : 2026-01-10 Size : 320kb User : hechunzhi99
[VHDL-FPGA-Verilog] button-controled-state-machine DL : 0: VHDL编的按键去抖，可以实现对目前的显示取反，即1、0、1、0 变换。-VHDL code of the key to shaking, can negate the current display, ie 1,0,1,0 transformation.
Date : 2026-01-10 Size : 223kb User : lucy
[VHDL-FPGA-Verilog] SRAM DL : 0: VerilogHDL语言读写SRAM内部数据。SRAM芯片型号为61WV102416ALL，即1024K字，每字16位，共16Mb。工作在100MHz频率下。-VerilogHDL language to read and write internal data SRAM. SRAM chip model 61WV102416ALL, ie 1024K words, each word 16, a total of 16Mb. Work in the 100MHz frequency.
Date : 2026-01-10 Size : 2kb User : 于潇宇
[VHDL-FPGA-Verilog] texisystem DL : 0: 以单片机为中央控制器，设计一台出租车计价系统。系统中的直流电源由车载电源提供，电源电压为+9V~+24V。行驶里程传感器不需要设计，假设它具有汽车每行使1km提供1000个脉冲信号的特性。显示器可以采用LED数码管或LCD液晶显示模块。应达到的技术指标： 1、白天、晚上分别设置不同的里程单价，两位数码显示“X.X”,并用一键控制转换及显示； 2、两位数码显示车辆行使的里程数“XX”； 3、营运起步价为5.00元，当小于3公里按起步价结算，当大于3公里时，按里程单价×里程数结算，并用三位数码显示“XX.X”； 4、一键控制总价清除及开始计价，即按一下系统开始计价，再按一下时总价被清除（即用按键模拟出租车上的“空车”指示牌功能）。 -Single-chip microcomputer as the central controller, the design of a taxi meter system. System in the DC source is vehicle power supply, power supply voltage of+9 V ~+24 V. No mileage sensor design, assuming it has a car 1km each exercise provides 1000 pulses features. LED digital tube display can be used or LCD display module. Should meet the technical specifications: 1, daytime, evening set different mileage unit, two digital display "XX", and conversion and with a key control Display 2, the exercise of two digital display vehicle mileage "XX" 3, the operation starting at 5.00 yuan, while less than 3 km at prices starting at settlement, when more than 3 km, priced according to mileage × mileage settlement, and with three digital display "XX.X" 4, a key control and began to clear the total valuation, that valuation system began clicking, and then click when the total is cleared (ie, simulated with a taxi on the button "empty" sign function).
Date : 2026-01-10 Size : 53kb User : yangzhen
[VHDL-FPGA-Verilog] texi DL : 0: 以单片机为中央控制器，设计一台出租车计价系统。系统中的直流电源由车载电源提供，电源电压为+9V~+24V。行驶里程传感器不需要设计，假设它具有汽车每行使1km提供1000个脉冲信号的特性。显示器可以采用LED数码管或LCD液晶显示模块。应达到的技术指标： 1、白天、晚上分别设置不同的里程单价，两位数码显示“X.X”,并用一键控制转换及显示； 2、两位数码显示车辆行使的里程数“XX”； 3、营运起步价为5.00元，当小于3公里按起步价结算，当大于3公里时，按里程单价×里程数结算，并用三位数码显示“XX.X”； 4、一键控制总价清除及开始计价，即按一下系统开始计价，再按一下时总价被清除（即用按键模拟出租车上的“空车”指示牌功能）。 -Single-chip microcomputer as the central controller, the design of a taxi meter system. System in the DC source is vehicle power supply, power supply voltage of+9 V ~+24 V. No mileage sensor design, assuming it has a car 1km each exercise provides 1000 pulses features. LED digital tube display can be used or LCD display module. Should meet the technical specifications: 1, daytime, evening set different mileage unit, two digital display "XX", and conversion and with a key control Display 2, the exercise of two digital display vehicle mileage "XX" 3, the operation starting at 5.00 yuan, while less than 3 km at prices starting at settlement, when more than 3 km, priced according to mileage × mileage settlement, and with three digital display "XX.X" 4, a key control and began to clear the total valuation, that valuation system began clicking, and then click when the total is cleared (ie, simulated with a taxi on the button "empty" sign function).
Date : 2026-01-10 Size : 73kb User : yangzhen
[VHDL-FPGA-Verilog] texismoke DL : 0: 以单片机为中央控制器，设计一台出租车计价系统。系统中的直流电源由车载电源提供，电源电压为+9V~+24V。行驶里程传感器不需要设计，假设它具有汽车每行使1km提供1000个脉冲信号的特性。显示器可以采用LED数码管或LCD液晶显示模块。应达到的技术指标： 1、白天、晚上分别设置不同的里程单价，两位数码显示“X.X”,并用一键控制转换及显示； 2、两位数码显示车辆行使的里程数“XX”； 3、营运起步价为5.00元，当小于3公里按起步价结算，当大于3公里时，按里程单价×里程数结算，并用三位数码显示“XX.X”； 4、一键控制总价清除及开始计价，即按一下系统开始计价，再按一下时总价被清除（即用按键模拟出租车上的“空车”指示牌功能）。 -Single-chip microcomputer as the central controller, the design of a taxi meter system. System in the DC source is vehicle power supply, power supply voltage of+9 V ~+24 V. No mileage sensor design, assuming it has a car 1km each exercise provides 1000 pulses features. LED digital tube display can be used or LCD display module. Should meet the technical specifications: 1, daytime, evening set different mileage unit, two digital display "XX", and conversion and with a key control Display 2, the exercise of two digital display vehicle mileage "XX" 3, the operation starting at 5.00 yuan, while less than 3 km at prices starting at settlement, when more than 3 km, priced according to mileage × mileage settlement, and with three digital display "XX.X" 4, a key control and began to clear the total valuation, that valuation system began clicking, and then click when the total is cleared (ie, simulated with a taxi on the button "empty" sign function).
Date : 2026-01-10 Size : 51kb User : yangzhen
[VHDL-FPGA-Verilog] xlgeneratebutton_example DL : 0: its a xlgenerator ie xilinx and matlab for cordic
Date : 2026-01-10 Size : 12kb User : sri karthik
[VHDL-FPGA-Verilog] serial DL : 0: 本模块的功能是验证实现和PC机进行基本的串口通信的功能。需要在PC机上安装一个串口调试工具来验证程序的功能。程序实现了一个收发一帧10个bit（即无奇偶校验位）的串口控制器，10个bit是1位起始位，8个数据位，1个结束位。串口的波特律由程序中定义的div_par参数决定，更改该参数可以实现相应的波特率。程序当前设定的div_par 的值是0x145，对应的波特率是9600。用一个8倍波特率的时钟将发送或接受每一位bit的周期时间划分为8个时隙以使通信同步.-The function of this module is to verify the basic serial communication and PC. Need to be installed on a PC with a serial debugging tools to verify the functionality of the program. The program implements a send and receive a 10-bit (ie, no parity bit) serial controller, 10 bit is a start bit, 8 data bits, 1 stop bit. The serial port s baud law determined by the procedures defined in div_par parameters, change the parameters to achieve the appropriate baud rate. The value of the procedures set div_par 0x145, corresponding to the baud rate is 9600. An eight times the baud rate clock to send or receive every bit of the cycle time is divided into eight time slots so that through Letter synchronization.
Date : 2026-01-10 Size : 55kb User : happy
[VHDL-FPGA-Verilog] LCD_display_frequency DL : 0: 频率计。具有4位显示，能自动根据7位十进制计数的结果，自动选择有效数据的--高4位进行动态显示。小数点表示是千位，即KHz。 -Frequency meter. With 4-digit display that can automatically count the results of seven decimal automatically select a valid data- high four dynamic display. That is a thousand decimal point, ie KHz.
Date : 2026-01-10 Size : 102kb User : 魏晖
[VHDL-FPGA-Verilog] qicheweideng DL : 0: 使用vhdl语言设计的汽车尾灯控制电路。用六个发光二极管模拟6个汽车尾灯（汽车尾部左,右各3个），用两个开关作为转弯控制信号（一个开关控制右转弯，另一个开关控制左转弯）。当汽车往前行驶时（此时两个开关的都未接通），6个灯全灭。当汽车转弯时，若右转弯（即右转开关接通），右边3个尾灯从左至右顺序亮灭，左边3个灯全灭；若左转弯（即左转开关接通），左边3个尾灯从右至左顺序亮灭，右边3个灯全灭。当左、右两个开关同时接通时，6个尾灯同时明、暗闪烁。 -The taillights control circuit using VHDL language design. Analog 6 automobile taillights (left of the rear of the car, the right of each 3) with six light emitting diodes, as a turn with the two switches the control signal (a switching control right turn, and another switch controls the left turn). When Previous traveling of the vehicle (when the two switches at this time none of ON), six light Quanmie. When the car turns, if the right turn (right turn switch is turned on), the right three taillights from left-to-right order of light off the left three light Quanmie left turn (ie turn left switch is turned on), the left The right-to-left order of a taillight light off, the right of three lights all off. When the left and right two switches simultaneously, 6 taillights and dark flashing.
Date : 2026-01-10 Size : 134kb User : 陈小龙
[VHDL-FPGA-Verilog] assigment3 DL : 0: Construct VHDL models for 74-139 dual 2-to-4-line decoders using three description styles, i.e., behavioral, dataflow and structural descriptions. Synthesize and simulate these models respectively in the environment of Xilinx ISE with the ModelSim simulator integrated. When simulating these models, test vector(s) are required to stimulate the units under test (UUT). Reasonable test vectors are designed and created by your own as sources added to your VHDL project.-Construct VHDL models for 74-139 dual 2-to-4-line decoders using three description styles, ie, behavioral, dataflow and structural descriptions. Synthesize and simulate these models respectively in the environment of Xilinx ISE with the ModelSim simulator integrated. When simulating these models, test vector (s) are required to stimulate the units under test (UUT). Reasonable test vectors are designed and created by your own as sources added to your VHDL project.
Date : 2026-01-10 Size : 303kb User : 胡珩
[VHDL-FPGA-Verilog] serial DL : 0: 本模块的功能是验证实现和PC机进行基本的串口通信的功能。需要在PC机上安装一个串口调试工具来验证程序的功能。程序实现了一个收发一帧10个bit（即无奇偶校验位）的串口控制器，10个bit是1位起始位，8个数据位，1个结束位。串口的波特律由程序中定义的div_par参数决定，更改该参数可以实现相应的波特率。程序当前设定的div_par 的值是0x104，对应的波特率是9600。用一个8倍波特率的时钟将发送或接受每一位bit的周期时间划分为8个时隙以使通信同步-The module' s function is to verify the basic realization and PC serial communication functions. Required on the PC to install a serial debugging tools to verify functionality of the program. Program implements a transceiver a 10 bit (ie, no parity bit) serial controller, 10 bit is a start bit, 8 data bits, 1 stop bit. Baud-law by the parameters defined in the program div_par decision to change the parameters of the corresponding baud rate can be achieved. Program is currently set div_par value is 0x104, corresponding to the baud rate is 9600. 8 times the baud rate with a transmit or receive clock cycle time of each bit is divided into eight time slots to the communication sync
Date : 2026-01-10 Size : 346kb User :
[VHDL-FPGA-Verilog] LabA1Design1 DL : 0: 设计求两数之差的绝对值电路：电路输入aIn、bIn为4位无符号二进制数，电路输出out为两数之差的绝对值，即out=|aIn-bIn|。要求用多层次结构设计电路，即调用数据选择器、加法器和比较器等基本模块来设计电路。-Design for the number two absolute value of the difference between circuits: circuit input aIn, bIn a 4-bit unsigned binary number, the circuit output out of the absolute value of the difference between the two numbers, ie out = | aIn-bIn |. Requires a multi-level structure design circuits that call data selector, adders and comparators, the basic module to design circuits.
Date : 2026-01-10 Size : 3kb User : Peter

« 12 »