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[VHDL-FPGA-Verilog] ClkScan DL : 0: 此设计采用Verilog HDL硬件语言设计,在掌宇开发板上实现. 将整个电路分为两个子模块，一个提供同步信号（H_SYNC和V_SYNC）及像素位置信息；另一个接收像素位置信息，并输出颜色信号。这样便于进行图形修改，同时也容易实现- This design uses Verilog the HDL hardware language design, realizes on the palm space development board Divides into two stature modules the entire electric circuit, provides the synchronized signal (H_SYNC and V_SYNC) and the picture element positional information; Another receive picture element positional information, and output color signal. Like this is advantageous for carries on the graph to revise, simultaneously is also easy to realize
Date : 2026-01-01 Size : 896kb User :
[VHDL-FPGA-Verilog] 100_vhdl_example DL : 0: 本书介绍了100个适用的VHDL源程序，并有仿真附图。-The book introduced the 100 applicable to VHDL source code, and have simulation graph.
Date : 2026-01-01 Size : 6.63mb User : 梁大法
[VHDL-FPGA-Verilog] fft DL : 0: 基于VHDL的FFT的实现,介绍FFT的软硬件实现,并有附图-The FFT based on the realization of VHDL to introduce hardware and software realization of FFT, and graph
Date : 2026-01-01 Size : 89kb User : 任杏
[VHDL-FPGA-Verilog] weisuijitu DL : 0: 伪随机图生成程序，包括时钟频率的合成、分别以比特和字节方式生成伪随机图模块。-Pseudo-random graph generation procedures, including the clock frequency synthesis means bits and bytes, respectively pseudo-random graph generation module.
Date : 2026-01-01 Size : 4kb User : 赵童
[VHDL-FPGA-Verilog] SPA DL : 0: 首先介绍了LDPC码的校验矩阵和其因子表示方法，然后利用二分图对和积解码算法进行了详细的描述，最后给出了信度传播概率译码算法详细步骤，并对关键公式作了证明-This paper,first introduces the check matrix and the factor graph of LDPC,then describes the sum-product algorithm by using the factor graph,and finally presents the detailed steps of the sum-product algorithm and gives a proof of certain important expressions.
Date : 2026-01-01 Size : 512kb User : 秦小星
[VHDL-FPGA-Verilog] divide_10 DL : 0: 十分频 quartus实现有RTL图-RTL is a graph realization of the frequency quartus
Date : 2026-01-01 Size : 1.03mb User : 海到无涯
[VHDL-FPGA-Verilog] sequence_dectect DL : 0: sequence_dect 实现6个状态，即6种选择的状态机。状态机的一个极度确切的描述是它是一个有向图形，由一组节点和一组相应的转移函数组成。-sequence_dectect to six states, namely, six options the state machine. State machine of an extremely precise description is that it is a directed graph, by a group of nodes and a corresponding transfer function form.
Date : 2026-01-01 Size : 1kb User : 吴海勇
[VHDL-FPGA-Verilog] graph-acceleration-verilog DL : 0: 2D图形加速，里面有串口模块。可以综合，为本人毕业设计。-2D graphics acceleration, which has the serial port module. Can be integrated, as my graduation project.
Date : 2026-01-01 Size : 1.07mb User : 吴帅
[VHDL-FPGA-Verilog] graph DL : 0: 六十进制计数器的源码，希望大家能支持下啊，谢谢啦。-no description
Date : 2026-01-01 Size : 155kb User : 谭玺
[VHDL-FPGA-Verilog] graph DL : 0: max+plus2 入门的模为12的计数器，测试过已经通过。-verilogHDL 12_counter
Date : 2026-01-01 Size : 16kb User : renwengang
[VHDL-FPGA-Verilog] 状态机 DL : 0: 本代码跟据状态转移图，通过verilog实现了一个有限状态机。(This code implements a finite state machine with the state transition graph through verilog.)
Date : 2026-01-01 Size : 180kb User : yuguofang