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[VHDL-FPGA-Verilog] n-thingeterroot DL : 0: Date : 2026-01-10 Size : 25kb User : zhang tian
[VHDL-FPGA-Verilog] Stage3_3175133_Zhang DL : 0: 用MATLAB里的XILINX BLOCKS, 支持FPGA算法, 实现X_NEXT = ((n-1)x+ A/x(n-1)次)/n
Date : 2026-01-10 Size : 28kb User : zhang tian
[VHDL-FPGA-Verilog] kvga2 DL : 0: Nondominated GA for optimization
Date : 2026-01-10 Size : 45kb User : vijay
[VHDL-FPGA-Verilog] fpga DL : 0: 基于现场可编程门阵列( Fie ld Programmab le Ga teA rrays, FPGA )硬件平台和背景差分算法设计一个静态背景下的视频移动目标检测与跟踪系统, 并详细给出系统的实现过程。检测结果表明: 采用FPGA硬件实现系统设计, 极大地提高了系统的处理速度, 在静态背景下, 可以实时、准确地检测和跟踪到移动目标。-Based on field programmable gate array (Fie ld Programmab le Ga teA rrays, FPGA) hardware platform and the background difference algorithm to design a static background Video moving target detection and tracking system, and details the system implementation process. Test results showed that: using FPGA hardware design, has greatly improved System processing speed, in a static background, in real time, to accurately detect and track moving targets.
Date : 2026-01-10 Size : 556kb User : chdj
[VHDL-FPGA-Verilog] New-Folder DL : 0: nhu lai than chung nhu con ga
Date : 2026-01-10 Size : 10kb User : nghia
[VHDL-FPGA-Verilog] Experiment08 DL : 0: FPGA源码，供初学者使用，时钟化和信号长度-GA source code, for beginners, clock and signal length
Date : 2026-01-10 Size : 1.2mb User : 李清政