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[VHDL-FPGA-Verilog] vhdlgenerateofsentencegrammarapplication DL : 0: vhdl实验计数器：generate语句的应用-Experimental VHDL Counter: generate statement application
Date : 2026-01-10 Size : 1kb User : 王天辉
[VHDL-FPGA-Verilog] Random_Number_generator DL : 0: 此代码用于产生系统设计仿真阶段需要的仿真数据，运行的结果是一系列随机数。编译后可生成数据产生模块，在其他工程中之间调用之作为数据输入即可，对vhdl涉及仿真有一定的帮助-This code is used for creating a system design simulation stage of simulation data, the results of running a series of random numbers. Compiler can generate data generated modules, in other works as a call between the data input to the VHDL simulation involves a certain degree of help
Date : 2026-01-10 Size : 35kb User : 王弋妹
[VHDL-FPGA-Verilog] work5FREQTEST DL : 0: 8位十六进制频率计设计根据频率的定义和频率测量的基本原理，测定信号的频率必须有一个脉宽为1s的输入信号脉冲计数允许信号；1s计数结束后，计数值被锁入锁存器，计数器清零，为下一测频计数周期做好准备。测频控制信号可由一个独立的发生器（FTCTRL）来产生。-8-bit hexadecimal Cymometer designed in accordance with the definition of frequency and frequency of the basic principles of measurement to determine the frequency of the signal must have a pulse width of the input signal for 1s permit pulse counting signal 1s counting after the total value was locked into the lock depositors, counters cleared for the next count cycle frequency measurement ready. Frequency control signal generator may be an independent (FTCTRL) to generate.
Date : 2026-01-10 Size : 239kb User : lkiwood
[VHDL-FPGA-Verilog] QuartusIIandModelSim DL : 0: 本文主要描述了如何在QUARTUS II 中输入程序文件，生成网表及标准延时文件，然后通过 MODELSIM进行功能仿真与后仿真的过程，主要为图解，含全部代码及仿真波形。 -This article describes how to enter at QUARTUS II program file, generate netlists and standard delay file, and then through the ModelSim for functional simulation and post-simulation process, mainly for the diagrams, containing all the code and the simulation waveform.
Date : 2026-01-10 Size : 271kb User : 朱雯
[VHDL-FPGA-Verilog] graphics_pipeline DL : 0: Implementation of GPU (Graphics Processing Unit) that rendered triangle based models. Our goal was to generate complex models with a movable camera. We wanted to be able to render complex images that consisted of hundreds to thousands of triangles. We wanted to apply interpolated shading on the objects, so that they appeared more smooth and realisitc, and to have a camera that orbitted around the object, which allowed us to look arond the object with a stationary light source. We chose to do this in hardware, because our initial implementation using running software on the NIOS II processor was too slow. Implementing parallelism in hardware is also easier to do than in software, which allows for more efficiency. We used Professor Land s floating point hardware, which allowed us to do calculations efficiency, which is essential to graphics.
Date : 2026-01-10 Size : 650kb User : Praveen
[VHDL-FPGA-Verilog] vga2 DL : 0: VHDL code for UP2 board of Altera, that generate a video signal to VGA port.
Date : 2026-01-10 Size : 325kb User : Lokous
[VHDL-FPGA-Verilog] FPGArealiztionofdigitalsignalprocessing DL : 0: 数字信号处理FPGA实现实用程序和文件,有sine.exe ---输入宽度。输出对应的正弦波表 mif文件 csd.exe --- 寻找整数和分数的标准有符号数字量（canonical signed digit ，CSD）表达式程序 fpinv.exe --- 倒数计算浮点数表的程序 dagen.exe ---分布式算法文件生成HDL" onclick="tagshow(event)" class="t_tag">VHDL代码的程序 cic.exe ---CIC滤波器计算参数的程序 -Digital Signal Processing FPGA realization of practical procedures and documents, there are sine.exe--- input width. Sine wave output of the corresponding csd.exe--- Table mif file to find the integer and fractional number of the volume of standard symbols (canonical signed digit, CSD) Expression Programming fpinv.exe--- countdown procedures for calculation of floating-point form dagen.exe--- documents distributed algorithm to generate HDL " onclick =" tagshow (event) " class =" t_tag " > VHDL program code cic.exe--- CIC filter process parameters
Date : 2026-01-10 Size : 254kb User : kevin
[VHDL-FPGA-Verilog] wavegenerator DL : 0: 开发环境为QuartusII，能产生正弦波、三角波、方波和锯齿波，幅度为5V，采样为8位，在开发板已经验证通过，有详细的波形图和管脚分配图。-Development environment for QuartusII, can generate sine wave, triangle wave, square wave and sawtooth wave, ranging from 5V, sampling for 8, in the development board has to verify is passed, the waveform in detail the distribution of maps and map pins.
Date : 2026-01-10 Size : 487kb User : 李海明
[VHDL-FPGA-Verilog] wtut_edif DL : 0: Xilinx clock. DIGITAL CLOCK for Spartan-3 Starter Board. This design shows how to generate a digital clock and display the output to the multiplexed 7- segment display in VHDL.
Date : 2026-01-10 Size : 20kb User : shad
[VHDL-FPGA-Verilog] PIPE_LINING_CPU_TEAM_24 DL : 0: 采用Quatus II编译环境，使用Verilog HDL语言编写实现了五段流水线CPU。能够完成以下二十二条指令（均不考虑虚拟地址和Cache，并且默认为小端方式）： add rd,rs,rt addu rd,rs,rt addi rt,rs,imm addiu rt,rs,imm sub rd,rs,rt subu rd,rs,rt nor rd,rs,rt xori rt,rs,imm clo rd,rs clz rd,rs slt rd,rs,rt sltu rd,rs,rt slti rt,rs,imm sltiu rt,rs,imm sllv rd,rt,rs sra rd,rt,shamt blez rs,imm j target lwl rt,offset(base) lwl rt,offset(base) lw rt,imm(rs) sw rt,imm(rs) 在本设计中，采取非常良好的模块化编程风格，共分十三个主要模块PIPE_LINING_CPU_TEAM_24.v为顶层实体文件，对应为PIPE_LINING_CPU_TEAM_24模块作为顶层实体模块，如下： ifetch.v、regdec.v、exec.v、mem.v、wr.v分别实现五个流水段； cpuctr.v用于产生CPU控制信号； ALU.v用于对操作数进行相应指令的运算并输出结果； DM.v数据存储器 IM.v指令存储器 datareg.v数据寄存器堆 extender.v位扩展 yiwei_32bits.v 实现32位四种移位方式的移位器在顶层实体中，调用ifetch.v、regdec.v、exec.v、mem.v、wr.v这五个模块就实现了流水线CPU。顶层模块的结构清晰明了。对于学习verilog编程非常有用- Quatus II compiled by the environment, using Verilog HDL language to achieve a five-stage pipeline CPU. To complete the following 22 commands (not considering the virtual address and Cache, and the default mode for the small end): add rd, rs, rt addu rd, rs, rt addi rt, rs, imm addiu rt, rs, imm sub rd, rs, rt subu rd, rs, rt nor rd, rs, rt xori rt, rs, imm clo rd, rs clz rd, rs slt rd, rs, rt sltu rd, rs, rt slti rt, rs, imm sltiu rt, rs, imm sllv rd, rt, rs sra rd, rt, shamt blez rs, imm j target lwl rt, offset (base) lwl rt, offset (base) lw rt, imm (rs) sw rt, imm (rs) In this design, take a very good modular programming style, is divided into 13 main modules PIPE_LINING_CPU_TEAM_24.v for the top-level entity file, the corresponding module as a top-level entity for the PIPE_LINING_CPU_TEAM_24 modules, as follows: ifetch.v, regdec.v, exec.v, mem.v, wr.v water were to achieve the five paragraph cpuctr.v used to generate CPU control signal ALU.v accordingly
Date : 2026-01-10 Size : 4.72mb User : 石
[VHDL-FPGA-Verilog] cpu DL : 0: 设计以及基本的CPU，至少包括四个基本单元，控制单元，内部寄存器，ALU和指令集-The purpose of this project is to design a simple CPU (Central Processing Unit). This CPU has basic instruction set, and we will utilize its instruction set to generate a very simple program to verify its performance. For simplicity, we will only consider the relationship among the CPU, registers, memory and instruction set. That is to say we only need consider the following items: Read/Write Registers, Read/Write Memory and Execute the instructions. At least four parts constitute a simple CPU: the control unit, the internal registers, the ALU and instruction set, which are the main aspects of our project design and will be studied.
Date : 2026-01-10 Size : 2.09mb User : mollyma
[VHDL-FPGA-Verilog] sram DL : 0: 数据存储和读取电路以一个双端口SRAM为中心，用二进制计数器产生存取地址、以十进制计数器产生欲存储的数据，读出的数据经过LED七段译码，送LED数码管显示-Data storage and reading circuit in a dual-port SRAM as the central access address generated using a binary counter to generate For decimal counter data stored, read out the data through LED seven-segment decoder, sending LED digital display
Date : 2026-01-10 Size : 424kb User : william
[VHDL-FPGA-Verilog] zidongpinlv DL : 0: 4位自动换挡数字频率计设计 1、由一个4位十进制数码管（含小数点）显示结果； 2、测量范围为1Hz~9999KHz； 3、能自动根据7位十进制的结果，自动选择有效数据的高4位进行动态显示（即量程自动转换），小数点表示是千位，即KHz； 4、为检测设计正确与否，应将时钟通过PLL和手控分频器产生宽范围的多个频率来测试自动换档频率计功能。 -4 automatic transmission design a digital frequency meter, by a 4 decimal digital tube (including the decimal point) shows the results 2, the measuring range 1Hz ~ 9999KHz 3, can automatically according to seven decimal results, automatically select valid data dynamic display of high 4 (ie, automatic range conversion), the decimal point that is 1000, which KHz 4, for the detection of design right or not, should be through the PLL and clock dividers generate wide range of manual multiple frequency Test automatic transmission frequency counter function.
Date : 2026-01-10 Size : 346kb User : 李伦特
[VHDL-FPGA-Verilog] viterbi DL : 0: This a code generator for some kinds of viterbi decoders. It can generate the synthesiable verilog HDL codes. These have been verified under simulation. The generator itself is released under GPL license but the Verilog HDL codes generated by it is without any restrictions except you MUST keep the license note in each Verilog HDL codes. I will be glad to head these Verilog HDL codes be used in some applications.-This is a code generator for some kinds of viterbi decoders. It can generate the synthesiable verilog HDL codes. These have been verified under simulation. The generator itself is released under GPL license but the Verilog HDL codes generated by it is without any restrictions except you MUST keep the license note in each Verilog HDL codes. I will be glad to head these Verilog HDL codes be used in some applications.
Date : 2026-01-10 Size : 639kb User : Nagendran
[VHDL-FPGA-Verilog] samlecode.vhdl DL : 0: THis code describes how to use the pwm singal generator and how to generate this using VHDL>
Date : 2026-01-10 Size : 17kb User : Jas
[VHDL-FPGA-Verilog] onepulse DL : 0: VHDL code for generate one pulse signal.
Date : 2026-01-10 Size : 19kb User :
[VHDL-FPGA-Verilog] ADSP2011Local DL : 0: pci9054芯片本地总线控制示例程序，可用于pci驱动和应用程序的测试。每隔一段时间产生一次中断，产生1，2，3等递增数据，配合pci9054驱动和应用程序完成数据传输 2.说明：文件夹内是Quartus 9.0的工程文件，使用Verilog语言。-pci9054 local bus control chip sample program can be used for pci driver and application testing. Generate an interrupt at regular intervals, resulting in increased data 1,2,3, etc., with pci9054 drivers and applications for data transmission 2 note: folders is Quartus 9.0 project file, use the Verilog language.
Date : 2026-01-10 Size : 4.67mb User :
[VHDL-FPGA-Verilog] vhdl-code-for-4-ring-counter DL : 0: this a simple code to generate 4-ring counter in vhdl. the test bench is also provided with ths code. a simple progrm
Date : 2026-01-10 Size : 11kb User : nasimus
[VHDL-FPGA-Verilog] VHDL DL : 0: 电路主要由七个模块组成：时钟产生模块用于产生1KHz的扫描时钟和1Hz的时钟；二分频模块用于对1Hz的时钟信号二分频；测量/校验选择模块用于功能选择；计数模块用于对输入的cp信号计数；送存选择、报警电路根据选择的量程送存信号并显示单位，在超出所选量程时报警；锁存器锁存要显示的结果；扫描显示模块在1KHz的扫描时钟下，依次扫描三个数码管，并显示结果。-The circuit consists of seven main modules: clock generation module is used to generate 1KHz scan clock and 1Hz clock frequency module for 1Hz clock signal frequency measurement/calibration selection module for function selection count module for the input the cp signal count deposit options, alarm deposit signal circuit according to the selected range and display units, within the selected range alarm latch latches to be displayed scanning display module at 1KHz the scan clock, scan the three digits, and displays the results.
Date : 2026-01-10 Size : 2kb User : 张骞
[VHDL-FPGA-Verilog] 0-999随机数 DL : 3: 1. 设计并实现一个随机数生成电路，每2秒随机生成一个0~999之间的数字，并在数码管上显示生成的随机数。 2. 为系统设置一个复位键，复位后数码管显示 “000”，2秒后再开始每2秒生成并显示随机数，要求使用按键复位。(1. Design and implement a random number generating circuit, which generates randomly every 2 seconds Form a number between 0 and 999 and display it on the nixie tube Generated random number. 2. Set a reset key for the system, and the nixie tube will display after reset "000", 2 seconds later, generate and display random every 2 seconds It is required to use the key to reset.)
Date : 2020-06-09 Size : 4.53mb User : Minbadly

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