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[VHDL-FPGA-Verilog] 同步FIFO设计 DL : 0: 用16*8 RAM实现一个同步先进先出（FIFO）队列设计。由写使能端控制该数据流的写入FIFO，并由读使能控制FIFO中数据的读出。写入和读出的操作由时钟的上升沿触发。当FIFO的数据满和空的时候分别设置相应的高电平加以指示。
Date : 2010-11-04 Size : 1.24mb User : lavien520@163.com
[VHDL-FPGA-Verilog] fifo的vhdl原代码 DL : 0: 本文为verilog的源代码-In this paper, the source code for Verilog
Date : 2025-12-23 Size : 22kb User : 艾霞
[VHDL-FPGA-Verilog] 一些VHDL源代码 DL : 0: 内有波形发生器，加法器，经典双进程状态机，伪随机熟产生器，相应加法器的测试向量，16×8bit RAM,FIFO,通用RAM等源程序-within waveform generator, Adder, classic dual-process state machine, cooked pseudo-random generator, the corresponding Adder test vector, 16 x 8bit RAM, FIFO, etc. source generic RAM
Date : 2025-12-23 Size : 44kb User : 蔡孟颖
[VHDL-FPGA-Verilog] my_ramlib_06 DL : 0: 包括各种类型存储器的VHDL描述，如FIFO，双口RAM等 -including various types of memory VHDL description, such as FIFO, Dual Port RAM, etc.
Date : 2025-12-23 Size : 601kb User : ruan
[VHDL-FPGA-Verilog] FIFO_BEFORE DL : 0: 是基于fpga的FIFO乒乓操作，后面是与SDRAM接口的，这样主要方便sdram的刷新-fpga is based on the FIFO Table Tennis operation, and is behind SDRAM interface, This major update to the convenience sdram
Date : 2025-12-23 Size : 207kb User : eva
[VHDL-FPGA-Verilog] my_fifo_vhdl DL : 0: XILINX的FPGA实现的双口ram源码，可作为dsp\SDRAM和pci桥接作用，可直接使用，实际工程通过。-XILINX FPGA Implementation of the dual-port ram source, as dsp \ SDRAM and pci bridge, and can be used directly, through practical projects.
Date : 2025-12-23 Size : 19kb User : 朱效志
[VHDL-FPGA-Verilog] ram DL : 0: 本原代码中利用VHDL语言编写了RAM、FIFO、ROM等常用的存储和缓冲部件，完全的代码在ALTERA的FPGA上已经通过仿真测试，保证可用.-primitive code using VHDL prepared RAM, FIFO, ROM, and other commonly used storage and buffer components, complete code in the Altera FPGA simulation test has been passed to ensure that available.
Date : 2025-12-23 Size : 2kb User : nick
[VHDL-FPGA-Verilog] Synthesizable_FIFO_verilog DL : 0: Synthesizable FIFO Model This example describes a synthesizable implementation of a FIFO. The FIFO depth and FIFO width in bits can be modified by simply changing the value of two parameters, `FWIDTH and `FDEPTH. For this example, the FIFO depth is 4 and the FIFO width is 32 bits.
Date : 2025-12-23 Size : 16kb User : lianlianmao
[VHDL-FPGA-Verilog] Verilog_FIFO_ram DL : 0: 一个可以综合的Verilog 写的FIFO存储器，word格式-An integrated Verilog wrote FIFO memory, word format
Date : 2025-12-23 Size : 19kb User : hjx
[VHDL-FPGA-Verilog] ramlib_06 DL : 0: 这是一个有关FIFO的VHDL 程序。。。请大家下载分享。-This is a FIFO of the VHDL program. . . Please download the U.S. share.
Date : 2025-12-23 Size : 564kb User : 张亚伟
[VHDL-FPGA-Verilog] VHDL-ram_fifo DL : 0: VHDL的ram和fifo model code 包含众多的厂家-VHDL the ram and fifo model code contains a large number of manufacturers
Date : 2025-12-23 Size : 1.6mb User : SL
[VHDL-FPGA-Verilog] fifo DL : 1: 用双端口ram实现异步fifo，采用格雷码，避免产生毛刺。-Using dual-port ram realize asynchronous fifo, the use of Gray code, avoiding the production of burr.
Date : 2025-12-23 Size : 1kb User : shili
[VHDL-FPGA-Verilog] connect20090223 DL : 0: fpga从FIFO读数据并上传到双口ram中。-FPGA read data from the FIFO and upload it to dual-port ram Medium.
Date : 2025-12-23 Size : 458kb User : 张菁
[VHDL-FPGA-Verilog] ram DL : 0: a 16 by 4 ram is used for many applications as a basic component such as fifo and stack etc
Date : 2025-12-23 Size : 1kb User : sri
[VHDL-FPGA-Verilog] fpga.fifo DL : 0: 异步FIFO是用来适配不同时钟域之间的相位差和频率飘移的重要模块。本文设计的异步FIFO采用了格雷（GRAY）变换技术和双端口RAM实现了不同时钟域之间的数据无损传输。该结构利用了GRAY变换的特点，使得整个系统可靠性高和抗干扰能力强，系统可以工作在读写时钟频率漂移达到正负300PPM的恶劣环境。并且由于采用了模块化结构，使得系统具有良好的可扩充性。-Asynchronous FIFO is an important module which always used to absorb the phase and frequency offset between different clock domain in communication area .In this paper, an FIFO module is designed using Gray convert technology and dual-port ram , which realizing scatheless transmit between different clock domain. The advances of Gray (Only one bit changes between neighboring two clock ) improves the reliability and anti-jamming capability of the system. And the system can work normally in the bad condition which the phase and frequency offset target to 300PPM. It is proved by work that the FIFO module can fulfill the demands of real-time of data transmitting system, and the module is powerful enough for more data process in the future.
Date : 2025-12-23 Size : 80kb User : 雷志
[VHDL-FPGA-Verilog] fifo_test DL : 0: FIFO读写verilog程序，经本人验证，能够顺利运行。实现FPGA对fifo的控制。-the example of writing and reading the fifo ram of the fpag,i have already tested it.
Date : 2025-12-23 Size : 2kb User : saul
[VHDL-FPGA-Verilog] FIFO DL : 0: 设计了一个具有双时钟信号，双复位信号的FIFO，用于FPGA中的数据缓冲，RAM的定义是参数型，可以根据自己的需求，修改此参数，完成RAM的容量扩展。程序中有详细的说明-Designed a dual-clock signal, double reset signal FIFO, for the FPGA in the data buffer, RAM is defined as parameter type, according to their needs, and modify this parameter, the completion of the capacity expansion of RAM. Procedures described in detail
Date : 2025-12-23 Size : 179kb User : luosheng
[VHDL-FPGA-Verilog] FPGA-Prototyping-by-VHDL-Examples---Xilinx-Sparta DL : 0: FPGA prototyping by VHDL examples include FIFO,RAM,ROM,filters, registers and others-FPGA prototyping by VHDL examples include FIFO,RAM,ROM,filters, registers and others
Date : 2025-12-23 Size : 15.85mb User : Aleks
[VHDL-FPGA-Verilog] ram_fifo_ram DL : 0: 程序实现了在FPGA内部开辟RAM+FIFO+RAM的IP核进行数据之间的调试。方便需要用到的童鞋进行参考。已通过modelsim调试-Implemented within the FPGA program to open up RAM+ FIFO+ RAM for data between the IP core debugging. Need to use the shoes for easy reference. Has passed debug modelsim
Date : 2025-12-23 Size : 7.81mb User : 袁官福
[VHDL-FPGA-Verilog] Synchronous FIFO DL : 0: 用16*8 RAM实现一个同步先进先出（FIFO）队列设计。由写使能端控制该数据流的写入FIFO，并由读使能控制FIFO中数据的读出。写入和读出的操作由时钟的上升沿触发。当FIFO的数据满和空的时候分别设置相应的高电平加以指示(mplementation of a synchronous first in first out (FIFO) queue design with 16*8 RAM. A write FIFO that controls the data stream by writing enable terminals and controls read of data in the FIFO by the read enable. The operation of writing and reading is triggered by the rising edge of the clock. When the data of FIFO is full and empty, set the corresponding high level to indicate)
Date : 2025-12-23 Size : 258kb User : 渔火

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