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[VHDL-FPGA-Verilog] qiangdaqi(auto) DL : 0: 用verilog hdl硬件描述语言实现多人抢答器功能，有计时，计分，报警等功能。-Using hardware description language verilog hdl people realize Answer feature, have timing, scoring and alarm functions.
Date : 2026-01-10 Size : 260kb User : 杨操
[VHDL-FPGA-Verilog] clock DL : 0: 利用xilin实验仪完成一个可以计时的数字时钟，显示范围位00.00～59.59，且该时钟应该具有暂停计时，清零灯功能。-Xilin completed experiment using a digital time clock, indicating the scope of digital 00.00 ~ 59.59, and the clock should have suspended time, Clear Lantern feature.
Date : 2026-01-10 Size : 79kb User : haolj
[VHDL-FPGA-Verilog] ETHERNET DL : 1: 具备GMII接口和ARP协议功能的千兆以太网控制器。经过Xilinx SPATAN-III FPGA验证, Verilog描述-With GMII interface and feature ARP protocol Gigabit Ethernet controller. After Xilinx SPATAN-III FPGA verification, Verilog description
Date : 2026-01-10 Size : 68kb User : winwalk
[VHDL-FPGA-Verilog] VHDL_infrared_receive DL : 0: VHDL程序，实现红外接收，解码，功能可扩展，入门者用-VHDL procedures realize infrared receiver, decoding, feature scalable, beginners to use
Date : 2026-01-10 Size : 2kb User : 小猪
[VHDL-FPGA-Verilog] myshizhong DL : 0: 该程序实现一个数字钟，带调整时间功能，在调整时间时，对应的位置闪烁显示。 CLR 为清零端，该键为‘1’时，时钟显示”000000“； EN 计数使能端，该键为‘1’时，时钟停止； MODE 模式选择按钮，在4种模式下循环：正常-小时调整-分调整-秒调整。 INC 调整时间按钮，该键为‘1’时，对应位置加1；-The program realization of a digital clock, adjust the time zone feature, adjust time, the location of the corresponding display flashes. CLR to zero client, the key to
Date : 2026-01-10 Size : 673kb User : 李东
[VHDL-FPGA-Verilog] ref-sqroot DL : 0: 開平方根IP將sqroot_license.txt中的FEATURE 6AF8_0048 alterad 0000.00 permanent uncounted 4A689178551B VENDOR_STRING=gl15kdhm5gUPkJD7iM82mn$$ HOSTID=ANY加入就可以使用了！-The square root of IP will be open sqroot_license.txt in FEATURE 6AF8_0048 alterad 0000.00 permanent uncounted 4A689178551B VENDOR_STRING = gl15kdhm5gUPkJD7iM82mn $ $ HOSTID = ANY can be used to join!
Date : 2026-01-10 Size : 39kb User : lin
[VHDL-FPGA-Verilog] VHDL DL : 0: 实现4种常见波形正弦、三角、锯齿、方波（A、B）的频率、幅度可控输出（方波 A的占空比也是可控的），可以存储任意波形特征数据并能重现该波形，还可完成各种波形的线形叠加输出。 -Realize four kinds of common sine wave, triangle, sawtooth, square wave (A, B) the frequency, magnitude controllable output (square wave A, is also a controllable duty cycle), can store arbitrary waveform feature data and can reproduce the waveform, but also completed a variety of linear superposition of the output waveform.
Date : 2026-01-10 Size : 9kb User : zhanyi
[VHDL-FPGA-Verilog] hdl DL : 0: cordic IC implement for fast cordic calculate. Including test bench. feature: 1. slicon proved. 2. support angle recored algorithm.-cordic IC implement for fast cordic calculate.Including test bench.feature: 1. slicon proved.2. support angle recored algorithm.
Date : 2026-01-10 Size : 8kb User : TTC
[VHDL-FPGA-Verilog] LED DL : 0: LED控制VHDL程序与仿真可以很好的实现功能-VHDL program LED control and simulation, you can achieve very good feature!
Date : 2026-01-10 Size : 5kb User : 唐光敏
[VHDL-FPGA-Verilog] VHDL-topics-Electronic-locks DL : 0: VHDL密码锁设计专题，学习使用VHDL设计密码锁-VHDL design of the password lock feature and learning to use the VHDL design code lock
Date : 2026-01-10 Size : 151kb User : 蔡宇佳
[VHDL-FPGA-Verilog] Fingerprint_Identify DL : 0: 本项目名称是：基于FPGA的指纹识别模块设计。主要内容为：本模块采用xilinx公司的Spartan 3E系列XC3S500E 型FPGA作为核心控制芯片，通过富士通公司的MFS300滑动式电容指纹传感器对指纹图象进行提取，然后对提取的指纹图像进行灰度滤波、图像增强、二值化、二值去噪、细化等预处理，得到清晰的指纹图象，再从清晰的指纹图象中提取指纹特征点，存入外部FLASH作为建档模板。指纹比对时，采用同样的方法获得清晰的指纹图像，建立比对模板，然后将比对模板与建档模板利用点模式匹配算法进行比对，得出比对结果。该模块利用嵌入式软核实现系统的管理，利用硬件实现指纹识别，保证了系统功能的完整性与识别的正确性。该识别模块可用于门禁、考勤、安检、保险箱柜等很多方面，也可和计算机等设备联机使用，满足各个方面的不同需求，因此它的设计具有很广泛的应用前景和市场价值。 -The project name is: FPGA-based fingerprint identification module design. The main contents are: the use of this module xilinx s Spartan 3E Series XC3S500E FPGA-based control chip as the core, through the MFS300 Fujitsu fingerprint slide sensor capacitance extraction of the fingerprint image, and then extracted gray-scale fingerprint image filtering, image enhancement, binarization, denoising Second, refinement, etc. pre-treatment have been given clear fingerprint image, and then a clear fingerprint image from the extracted fingerprint feature points, into the external FLASH file as a template. Fingerprint matching using the same method to obtain a clear image of the fingerprint to establish than the template, and then will be the template file templates and the use of point pattern matching algorithm than the right, than the results obtained. The module is the realization of the use of soft-core embedded system management, the use of fingerprint recognition hardware implementation
Date : 2026-01-10 Size : 187kb User : xiaoxu
[VHDL-FPGA-Verilog] LatticeMico8_v3_0_Verilog DL : 0: The LatticeMico8™ is an 8-bit microcontroller optimized for Field Programmable Gate Arrays (FPGAs) and Crossover Programmable Logic Device architectures from Lattice. Combining a full 18-bit wide instruction set with 16 or 32 General Purpose registers, the LatticeMico8 is a flexible Verilog and VHDL reference design suitable for a wide variety of markets, including communications, consumer, computer, medical, industrial, and automotive. The core consumes minimal device resources, less than 200 Look Up Tables (LUTs) in the smallest configuration, while maintaining a broad feature set.-The LatticeMico8™ is an 8-bit microcontroller optimized for Field Programmable Gate Arrays (FPGAs) and Crossover Programmable Logic Device architectures from Lattice. Combining a full 18-bit wide instruction set with 16 or 32 General Purpose registers, the LatticeMico8 is a flexible Verilog and VHDL reference design suitable for a wide variety of markets, including communications, consumer, computer, medical, industrial, and automotive. The core consumes minimal device resources, less than 200 Look Up Tables (LUTs) in the smallest configuration, while maintaining a broad feature set.
Date : 2026-01-10 Size : 1.1mb User : 郭豪偉
[VHDL-FPGA-Verilog] edaVHDL DL : 0: 数字系统与VHDL程序设计语言非常高速硬件描述语言, 也就是一种硬件(数字电路)设计语言. 其最大特点是对电路的行为与结构进行高度抽象化规范化，并对设计进行模拟验证与综合优化，使分析和设计高度自动化。 -Digital systems with VHDL programming language very high speed hardware description language, which is a hardware (digital circuit) design language. Its most prominent feature of the circuit behavior and structure of a high degree of standardization of the abstract, and simulation design and synthesis optimization so that the analysis and design of a high degree of automation.
Date : 2026-01-10 Size : 4.59mb User : liz
[VHDL-FPGA-Verilog] uart_tx_rx DL : 0: 该工程用verilog编写，已通过串口调试助手调试通过，接收模块采用8倍波特率采样数据，有较好的滤波功能，在PC上完成自发自收功能。-Verilog prepared by the project, has passed through the serial debug debugging assistant, receiving 8 times the baud rate module sampling data, a better filtering in the PC to complete the voluntary self-close feature.
Date : 2026-01-10 Size : 1.25mb User : eric
[VHDL-FPGA-Verilog] FPGA-DDS DL : 1: 在FPGA内，以查表方式实现频率直接合成器（DDS）功能。verilog源代码-In the FPGA in order to achieve the look-up table means the direct synthesizer frequency (DDS) feature. verilog source code
Date : 2026-01-10 Size : 2kb User : niuqs
[VHDL-FPGA-Verilog] ddsm DL : 0: 用vhdl实现dds功能的程序试一试看看是不适合你！-Dds feature using vhdl program to try to achieve a look is not for you!
Date : 2026-01-10 Size : 1kb User : maxmilian
[VHDL-FPGA-Verilog] waveform-generator-o-VHDL-program DL : 0: 实现4种常见波形正弦、三角、锯齿、方波（A、B）的频率、幅度可控输出（方波 --A的占空比也是可控的），可以存储任意波形特征数据并能重现该波形，还可完成 --各种波形的线形叠加输出。 -Achieve the four kinds of common sine wave, triangle, sawtooth, square wave (A, B) the frequency and amplitude controlled output (square wave- A duty cycle is controlled), can store arbitrary waveform feature data and can to reproduce the waveform, it can perform- all kinds of linear superposition of the output waveform.
Date : 2026-01-10 Size : 10kb User : 刘新
[VHDL-FPGA-Verilog] 4bitcomparator DL : 0: FPGA实现四位比较器功能 -FPGA realization of four feature comparison
Date : 2026-01-10 Size : 87kb User : 石义敏
[VHDL-FPGA-Verilog] sram DL : 0: 基于FPGA的SRAM控制程序，里面附加了在线逻辑分析功能的程序，调试时相当的方便-SRAM-based FPGA-control program, which added an online feature of the program logic analysis, debugging very convenient when
Date : 2026-01-10 Size : 1.67mb User : 李成有
[VHDL-FPGA-Verilog] fir_filter DL : 0: 使用Verilog编程实现的分布式FIR滤波器源码，经过调试能够完成功能-Distributed programming using the Verilog source code FIR filters, after a debugging feature to complete
Date : 2026-01-10 Size : 14kb User : lisa1027

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