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[VHDL-FPGA-Verilog] SystemC_for_SOC DL : 0: 为了辅助大家学习《SystemC片上系统设计》一书，方便大家阅读、理解、实践SystemC。大部分代码在Microsoft Visual Studio 6.0上编译通过，另有一些代码无法在个人电脑上使用，可以在工作站的Sun Solaris上编译通过。建议大家带着批评而不是崇拜的眼光来学习这些代码。 SystemC Core Language library 201是SystemC核心语言库，可以在个人电脑上运行。 SystemC MasterSlave Library201是SystemC核心Master/Slave库，可以在个人电脑上运行。这两个库在运行前需要编译。-In order to assist them to learn " SystemC SoC design," a book so as to facilitate reading, understanding, practice SystemC. Most of the code in Microsoft Visual Studio 6.0 on the compile, while some code can not be used in personal computers, workstations, Sun Solaris can be compiled through. Suggest that you not worship with the eyes of critics to learn the code. SystemC Core Language library 201 is the SystemC core language library that can be run on personal computers. SystemC MasterSlave Library201 is the core SystemC Master/Slave Library, can be run on personal computers. The two libraries to compile before running.
Date : 2025-12-26 Size : 2.34mb User :
[VHDL-FPGA-Verilog] div_f DL : 0: --学习分频原理，在LED上面显示出来。一亮一暗 --利用计数器分频，把50MHZ的频率变的更慢。我们眼睛可以分辨的出来。 --输出是1Hz-- Learning divider principle, above the LED display.- The use of counter divider light up a dark 50MHZ frequency becomes slower. Our eyes can distinguish.- Output is 1Hz
Date : 2025-12-26 Size : 1kb User : lixiaolong