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[VHDL-FPGA-Verilog] CPLD的跑馬燈 DL : 0: cpld的入门交流：CPLD的跑馬燈一个简易型cpld试验电路用VHDL语言遍的-cpld entry exchange : CPLD 5,250 cpld an easy-to-use test circuit using VHDL times the
Date : 2025-12-22 Size : 63kb User : 口是心非
[VHDL-FPGA-Verilog] (7.27)final_cbb01 DL : 0: 网络中交换节点的上数据的交换和下行数据分发的硬件实现-network nodes to exchange data on the downlink data exchange and distribution of hardware
Date : 2025-12-22 Size : 288kb User : 茜茜
[VHDL-FPGA-Verilog] 32fenpinqi DL : 0: 这是用VHDL语言写的32位分频器的程序，可直接运行，看结果，欢迎使用。多指正，交流。-This is written in VHDL 32 dividers procedures can be run directly see the results, welcomed the use. More correct exchange.
Date : 2025-12-22 Size : 12kb User : 刘彦平
[VHDL-FPGA-Verilog] CePQ DL : 0: 测频器，用VHDL语言编写。新手学习作品，还有好多不完善的地方，全当交流，也希望能下载本站原码学习。-frequency measurement device using VHDL language. Rookie learning works, there are a lot of imperfections, when the whole exchange, and hope they can download the original code study site.
Date : 2025-12-22 Size : 417kb User : 屈峥
[VHDL-FPGA-Verilog] run_length_coding DL : 0: 用verilog 编写应用于图像压缩编码中使用行程长度编码(run lengthencoding,RLE)对交流系数(Aa)进行编码。-using Verilog prepared for image compression coding using length encoding (run leng thencoding, RLE) on the exchange coefficient (Aa) coding.
Date : 2025-12-22 Size : 9kb User : 周信均
[VHDL-FPGA-Verilog] fpgavhdldaima DL : 0: 用VHDL语言编写的代码，以供大家学习和交流，方便大家学习！-prepared using VHDL code for all to study and exchange to facilitate learning!
Date : 2025-12-22 Size : 4kb User : 和尚
[VHDL-FPGA-Verilog] tbxsp010 DL : 0: 用VHDL语言编写的代码，以供大家学习和交流，方便大家学习！-prepared using VHDL code for all to study and exchange to facilitate learning!
Date : 2025-12-22 Size : 26kb User : 和尚
[VHDL-FPGA-Verilog] RS_decoder DL : 0: rs编码vvhdl 希望能通过我不晓得具体对大家有用否希望懂rs编码的多多交流 -rs coding vvhdl I do not want to be able to know the specific useful whether you want to understand a lot of coding rs exchange
Date : 2025-12-22 Size : 15kb User :
[VHDL-FPGA-Verilog] traffic_controller DL : 0: 这是使用VHDL编写的交通灯程序,供大家交流学习-This is the use of VHDL prepared by the traffic lights procedures for the exchange of learning
Date : 2025-12-22 Size : 216kb User : 黄鹏飞
[VHDL-FPGA-Verilog] iictestbench DL : 0: vhdl写的完整i2c代码,有仿真文件,是清华的人写的,质量可靠,请大家交流,qq:398087764-vhdl the integrity i2c write code, simulation document, the writers of Qinghua, reliable quality, Please exchange qq : 398087764
Date : 2025-12-22 Size : 209kb User : sunwei
[VHDL-FPGA-Verilog] VHDL_of_example DL : 0: 此为 VHDL 的示例程序,由于最近毕业设计要求使用这个编程,自己收集并整理了一些,供学习使用,希望和大家共同进步,有兴趣的也希望能和我一起讨论交流-this as examples of VHDL procedures, due to the recent graduation design requirements using the program, their collection by some for learning, hope and common progress. Interested also hoped to be able to discuss and exchange I
Date : 2025-12-22 Size : 51kb User : 钟毓秀
[VHDL-FPGA-Verilog] vhdlduogelizi DL : 0: 多个VHDL程序,跟大家参考,交流,谢谢,了,大家 -many VHDL procedures, with reference exchange, thank you, and we
Date : 2025-12-22 Size : 313kb User : 可耕地
[VHDL-FPGA-Verilog] sdr_data_path DL : 0: SDRAM控制器Verilog员代码，数据链路模块，完成和顶层模块的数据交换-SDRAM controller member Verilog code, data link module, Top module completed and the data exchange
Date : 2025-12-22 Size : 2kb User : 陈建勇
[VHDL-FPGA-Verilog] spi DL : 0: VHDL实现SPI功能源代码 -- The SPI bus is a 3 wire bus that in effect links a serial shift -- register between the "master" and the "slave". Typically both the -- master and slave have an 8 bit shift register so the combined -- register is 16 bits. When an SPI transfer takes place, the master and -- slave shift their shift registers 8 bits and thus exchange their 8 -- bit register values.-SPI realize the functional VHDL source code The SPI bus is a 3 wire bus that in effect links a serial shift register between the
Date : 2025-12-22 Size : 64kb User : 阿飞
[VHDL-FPGA-Verilog] ps2 DL : 0: ＰＳ／２通讯协议是一种双向同步串行通讯协议。通讯的两端通过Ｃｌｏｃｋ（时钟脚）同步，并通过Ｄａｔａ（数据脚）交换数据。任何一方如果想抑制另外一方通讯时，只需要把Ｃｌｏｃｋ（时钟脚）拉到低电平。一般两设备间传输数据的最大时钟频率是３３ｋＨｚ，大多数ＰＳ／２设备工作在１０～２０ｋＨｚ。推荐值在１５ｋＨｚ左右，也就是说，Ｃｌｏｃｋ（时钟脚）高、低电平的持续时间都为４０μｓ。每一数据帧包含１１～１２个位。 -PS/2 communication protocol is a bi-directional synchronous serial communication protocol. Communication at both ends through the Clock (the clock pin) synchronization, and Data (data pin) to exchange data. If you want to inhibit any of the parties the other party of communication, just to Clock (Clock feet) down low. The general transmission of data between two devices of the maximum clock frequency is 33kHz, the majority of PS/2 devices work in the 10 ~ 20kHz. Recommended value of around 15kHz, which means, Clock (Clock feet) high, low for the duration of 40μs. Each data frame contains 11 ~ 12-bit.
Date : 2025-12-22 Size : 1kb User :
[VHDL-FPGA-Verilog] vhdl DL : 0: 经典双进程状态机（含test beach）,很好的内容,供大家学习交流-Classic two-process state machine (including the test beach), very good content for everyone to study the exchange of
Date : 2025-12-22 Size : 1kb User : 吴风昱
[VHDL-FPGA-Verilog] UART DL : 0: 用FPGA实现了RS232异步串行通信，所用语言是VHDL，另外本人还有Verilog的欢迎交流学习，根据RS232 异步串行通信来的帧格式，在FPGA发送模块中采用的每一帧格式为：1位开始位+8位数据位+1位奇校验位+1位停止位，波特率为2400。由设置的波特率可以算出分频系数，具体算法为分频系数X=CLK/(BOUND*2)。-Using FPGA to achieve the RS232 asynchronous serial communication, the language used is VHDL, In addition, I also welcome the exchange of learning Verilog, according to RS232 asynchronous serial communication to the frame format, in the FPGA module used to send each frame format : the beginning of a bit+ 8-bit data bit+ 1 bit odd parity bit+ 1 bit stop bit, baud rate for 2400. By setting the baud rate can be calculated at the frequency coefficient, the specific algorithm for the sub-frequency coefficient X = CLK/(BOUND* 2).
Date : 2025-12-22 Size : 1kb User : saibei007
[VHDL-FPGA-Verilog] lingmindu DL : 0: 心电图机中灵敏度控制的VHDL代码，想交流的加我QQ147440013-ECG sensitivity control VHDL code, plus I would like to exchange QQ147440013
Date : 2025-12-22 Size : 3kb User : 黄建
[VHDL-FPGA-Verilog] ref-sdr-sdram-verilog DL : 0: 标准SRD SDRAM控制器参考设计，altera提供 Verilog代码,带有使用手册，大家试试交流一下 -Standard SRD SDRAM controller reference design, altera provide Verilog code, with user manual, we try to exchange some
Date : 2025-12-22 Size : 758kb User : 费尔德
[VHDL-FPGA-Verilog] TEST5 DL : 0: 这个是秒表的程序,很简单,不要取笑,多多交流了-This is a stopwatch procedures, is very simple, do not make fun of, a lot of exchange of
Date : 2025-12-22 Size : 1kb User : chen

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