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[VHDL-FPGA-Verilog] 74LS164 DL : 0: 大多数电子爱好者可能都有一个共同的感触就是显示部分会占用我们MCU大量的IO资源，LCD1602也不例外。本资料就是利用74LS164解决LCD1602这个问题的-Most e-lovers may have a common feeling is that we show part of the MCU will occupy a lot of IO resources, LCD1602 is no exception. This information is used 74LS164 solve this problem LCD1602
Date : 2026-01-03 Size : 4kb User : linjian
[VHDL-FPGA-Verilog] DE2_LCM_CCD_detect_b DL : 1: 本程序基于Altera公司的DE2平台完成仓库的实时监控并对移动的目标进行自动识别和报警的FPGA设计，研究重点就是图像采集和移动目标识别的FPGA实现。采用Altera公司的DC2模版对视频进行采集并将采集到的图像信息进行缓存，通过监视器实时显示，采用帧间差分法对采集到的帧图像进行运动检测，当仓库中有运动情况的时候，两个图像间灰度会出现异常，通过对灰度异常的侦测完成仓库移动目标的识别并蜂鸣器报警。-Complete real-time monitoring of the warehouse and moving target based on the Altera DE2 platform FPGA design of automatic identification and alarm, the research focus of the image acquisition and recognition of the moving target FPGA implementation. Altera Corporation DC2 template image acquisition and acquisition information to cache the video monitor real-time display, inter-frame difference method for motion detection frames collected, when the movement in the warehouse. between the gray scale in the two images will be abnormal, the warehouse moving target identification grayscale exception detection and buzzer alarm.
Date : 2026-01-03 Size : 18.58mb User : wangyi
[VHDL-FPGA-Verilog] PIPELINE DL : 1: （包含详细说明文档和简单汇编转机器码翻译器）五级流水线实现MIPS指令集（30条）含异常处理。结构采用多分支预测结构（基于历史的动态分支预测）-(Contains detailed documentation and compilation turn simple machine code translator) five pipelined MIPS instruction set (30) with exception handling. Structure using multi-branch prediction structure (based on the dynamic branch prediction history)
Date : 2026-01-03 Size : 1.11mb User : yuxueru
[VHDL-FPGA-Verilog] Coding Files DL : 0: Floating Point FP multiplication is widely used in large set of scientific and signal processing computation. Multiplication is one of the common arithmetic operations in these computations. A high speed floating point double precision multiplier is implemented on a Virtex 6 FPGA. In addition, the proposed design is compliant with IEEE 754 format and handles over flow, under flow, rounding and various exception conditions. The design achieved the operating frequency of 414.714 MHz with an area of 648 slices.
Date : 2026-01-03 Size : 51kb User : kutti