Search - epm7128

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[VHDL-FPGA-Verilog] cpld_bus DL : 0: Date : 2025-12-21 Size : 213kb User : hamlemon
[VHDL-FPGA-Verilog] Digital_030423 DL : 0: 服务器的的板在载控制器的AHDL程序,包括原理图编译,用在EPM7128上(CPLD).-server board controller is contained in the AHDL procedures, including schematic compiler, the use EPM7128 (CPLD).
Date : 2025-12-21 Size : 514kb User : 老罗
[VHDL-FPGA-Verilog] VHDL-Clock DL : 0: 用VHDL语言写的时钟程序。采用模块化编程。可在EPM7128芯片上下载。编译环境可用Maxplus或Quartus。-write VHDL clock procedures. Modular programming. The EPM7128 chips download. Build environment or Quartus Maxplus available.
Date : 2025-12-21 Size : 4kb User : 单单
[VHDL-FPGA-Verilog] cpldPWM DL : 0: verilog HDL 编写的PWM，是初学CPLD者入门Z资源，epm7128stc100-10-verilog HDL prepared by the PWM, is a novice CPLD Getting Started Z resources, epm7128stc100-10
Date : 2025-12-21 Size : 231kb User : 章风
[VHDL-FPGA-Verilog] lctl_1.2 DL : 0: CPLD的例子程序1,EPM7128芯片,ISA总线-Examples of CPLD procedures 1, EPM7128 chip, ISA Bus
Date : 2025-12-21 Size : 212kb User : Sean Cheung
[VHDL-FPGA-Verilog] spi DL : 0: 用vhdl编写的spi接口程序，在epm7128上仿真成功。-VHDL prepared using spi interface program, in the simulation epm7128 success.
Date : 2025-12-21 Size : 1kb User : 邓立新
[VHDL-FPGA-Verilog] EPM7128TMS320LF2407A DL : 0: emp7128在电平转换中的应用希望大家下载，必定收益-Level Translators in emp7128 Application hope everyone downloads, certainly proceeds
Date : 2025-12-21 Size : 22kb User : q
[VHDL-FPGA-Verilog] music DL : 0: 设计并调试好一个能产生”梁祝”曲子的音乐发生器，并用EDA实验开发系统（拟采用的实验芯片的型号可选Altera的MAX7000系列的 EPM7128 CPLD ，FLEX10K系列的EPF10K10LC84-3 FPGA， ACEX1K系列的 EP1K30 FPGA，Xinlinx 的XC9500系列的XC95108 CPLD，Lattice的ispLSI1000系列的1032E CPLD）进行硬件验证。设计思路根据系统提供的时钟源引入一个12MHZ时钟的基准频率，对其进行各种分频系数的分频，产生符合某一音乐的频率，然后再引入4HZ的时钟为音乐的节拍控制，最后通过扬声器放出来。 -Design and debug a good one can produce The Butterfly Lovers piece of music generator, and the development of EDA experimental system (to be used in models of experimental chip with optional Altera s MAX7000 series EPM7128 CPLD, FLEX10K series EPF10K10LC84-3 FPGA, ACEX1K Series The EP1K30 FPGA, Xinlinx the XC9500 series XC95108 CPLD, Lattice s ispLSI1000 series 1032E CPLD) for hardware verification. Design according to the system clock source provided by the introduction of a benchmark 12Mhz clock frequency and its various sub-sub-band frequency coefficients, resulting in consistent with the frequency of a particular music, and then the introduction of 4Hz clock control for the music beats, and finally through Loudspeakers released.
Date : 2025-12-21 Size : 8kb User : lijq
[VHDL-FPGA-Verilog] colorful_signal DL : 0: 设计并调试好一个VGA彩条信号发生器，并用EDA实验开发系统（拟采用的实验芯片的型号可选Altera的MAX7000系列的 EPM7128 CPLD ，FLEX10K系列的EPF10K10LC84-3 FPGA， ACEX1K系列的 EP1K30 FPGA，Xinlinx 的XC9500系列的XC95108 CPLD，Lattice的ispLSI1000系列的1032E CPLD）进行硬件验证。设计思路由系统提供的时钟源引入扫描信号，根据VGA彩色显示器的工作原理，设计出各种颜色编码和行场扫描信号。将并口线从计算机并口与CPLD/FPGA适配板连接好，然后将VGA接口与彩色显示器连接好，彩条信号就可以在显示器中产生，通过按键可以改变产生彩条的方式，共六种彩条信号，两种横彩条，两种竖彩条，两种棋盘格。本实验运用层次化设计出VGA彩条信号发生器，由行场信号模块模块和彩条信号发生模块构成，彩条信号发生器的顶层原理图如图10.7 所示. -err
Date : 2025-12-21 Size : 7kb User : lijq
[VHDL-FPGA-Verilog] 48led DL : 0: 此软件用的是QuartusII 5.1的环境编写的CPLD内的程序，CPLD用的是EPM7128，实现的功能是对计算机的ISA总线读写操作，计算机通过ISA总线，再通过CPLD，来控制LED的亮和灭-This software is used in the preparation of QuartusII 5.1 environment within the CPLD procedures, CPLD using EPM7128, the function of the realization of the ISA bus on the computer to read and write operation, the computer through the ISA bus, and then through the CPLD, to control the LED' s Liang and poverty
Date : 2025-12-21 Size : 197kb User : hujianhua
[VHDL-FPGA-Verilog] cpld1 DL : 0: 简易逻辑分析仪的vhdl程序，用于epm7128经测试可用-Simple logic analyzer vhdl procedure
Date : 2025-12-21 Size : 1.39mb User : 朱亚东洋
[VHDL-FPGA-Verilog] DDS DL : 0: 基于EPM7128的数字合成信号发生器（DDS）设计。通过对EPM7128编程，组合出地址累加器、数据锁存器、256*8位ROM空间。外接DA可实现正弦波输出功能-EPM7128-based signal generator for digital synthesis (DDS) design. EPM7128 through programming, the combination of address accumulator, data latches, 256* 8 ROM space. DA external sine wave output function can be realized
Date : 2025-12-21 Size : 346kb User : xiaoyu
[VHDL-FPGA-Verilog] jtagdownload DL : 1: alter cpld下载线制作方法集合，自己做就行，不用花40元去买了-alter cpld download cable production method of collection, make their own on the line, do not have to spend 40 yuan to buy a
Date : 2025-12-21 Size : 2.34mb User : 高兵
[VHDL-FPGA-Verilog] cpld_sy03091 DL : 0: cpld epm7128开发板原理图源程序资料-cpld epm7128 information source development board schematics
Date : 2025-12-21 Size : 1.22mb User : zhaoshihai
[VHDL-FPGA-Verilog] CPLD7128q DL : 0: EPM7128实现的总线扩展，以及ad采集等功能。-EPM7128 bus extension implementation, and the ad acquisition functions.
Date : 2025-12-21 Size : 561kb User : liliugang
[VHDL-FPGA-Verilog] cpld--abcount090418 DL : 0: epm7128做的24位硬件计数器，频率根据cpld 的晶振决定上限。-epm7128 do 24-bit hardware counter, the oscillator frequency according to the decision cpld ceiling.
Date : 2025-12-21 Size : 307kb User : liliugang
[VHDL-FPGA-Verilog] matlab-gmsk DL : 1: 基于matlab和vhdl的通信原理gmsk调制算法，主要包括GMSK相位路径的计算,GMSK眼图的仿真以验证相位计算的正确性,正余弦表的量化及bin文件的生成,以及用VHDL硬件语言所描述的基于EPM7128的地址逻辑.-Matlab and vhdl based on the principle gmsk Modulation of communication, including GMSK phase path calculation, GMSK eye diagrams of the simulation to verify the correctness of the phase calculation, is the cosine table generating quantitative and bin files, and using VHDL hardware description language logic based on the address of EPM7128.
Date : 2025-12-21 Size : 450kb User : zenpging
[VHDL-FPGA-Verilog] bahe DL : 0: 在EPM7128板上实现一个拔河游戏机，k1，k5是双方控制按钮，led灯模拟绳子状态-The realization of a tug of war in EPM7128 board game, k1, k5 is both control buttons, led rope lights simulate the state
Date : 2025-12-21 Size : 75kb User : 韦楠
[VHDL-FPGA-Verilog] tanchishe DL : 0: 数字电路与逻辑设计综合实验，贪吃蛇游戏机的实验报告。本实验是用通过VHDL的代码编写，然后下载到EPM7128数字逻辑实验开发板上，用点阵显示老鼠，蛇，以及墙，用数码管显示倒计时以及得分的情况。最终实现老鼠的随机出现，蛇的移动以及吃老鼠得分，撞墙或触边即死。-Digital circuit and logic design experiment, experimental report of the Snake game consoles
Date : 2025-12-21 Size : 256kb User : 张三